0001 Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
0002
0003 Required properties:
0004 - compatible: value should be one of the following:
0005 "atmel,at91sam9n12-hlcdc"
0006 "atmel,at91sam9x5-hlcdc"
0007 "atmel,sama5d2-hlcdc"
0008 "atmel,sama5d3-hlcdc"
0009 "atmel,sama5d4-hlcdc"
0010 "microchip,sam9x60-hlcdc"
0011 - reg: base address and size of the HLCDC device registers.
0012 - clock-names: the name of the 3 clocks requested by the HLCDC device.
0013 Should contain "periph_clk", "sys_clk" and "slow_clk".
0014 - clocks: should contain the 3 clocks requested by the HLCDC device.
0015 - interrupts: should contain the description of the HLCDC interrupt line
0016
0017 The HLCDC IP exposes two subdevices:
0018 - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
0019 - a Display Controller: see ../display/atmel/hlcdc-dc.txt
0020
0021 Example:
0022
0023 hlcdc: hlcdc@f0030000 {
0024 compatible = "atmel,sama5d3-hlcdc";
0025 reg = <0xf0030000 0x2000>;
0026 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
0027 clock-names = "periph_clk","sys_clk", "slow_clk";
0028 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
0029
0030 hlcdc-display-controller {
0031 compatible = "atmel,hlcdc-display-controller";
0032 pinctrl-names = "default";
0033 pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036
0037 port@0 {
0038 #address-cells = <1>;
0039 #size-cells = <0>;
0040 reg = <0>;
0041
0042 hlcdc_panel_output: endpoint@0 {
0043 reg = <0>;
0044 remote-endpoint = <&panel_input>;
0045 };
0046 };
0047 };
0048
0049 hlcdc_pwm: hlcdc-pwm {
0050 compatible = "atmel,hlcdc-pwm";
0051 pinctrl-names = "default";
0052 pinctrl-0 = <&pinctrl_lcd_pwm>;
0053 #pwm-cells = <3>;
0054 };
0055 };
