0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # # Copyright (c) 2021 Aspeed Tehchnology Inc.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Aspeed Low Pin Count (LPC) Bus Controller
0009
0010 maintainers:
0011 - Andrew Jeffery <andrew@aj.id.au>
0012 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
0013
0014 description:
0015 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
0016 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
0017 primary use case of the Aspeed LPC controller is as a slave on the bus
0018 (typically in a Baseboard Management Controller SoC), but under certain
0019 conditions it can also take the role of bus master.
0020
0021 The LPC controller is represented as a multi-function device to account for the
0022 mix of functionality, which includes, but is not limited to
0023
0024 * An IPMI Block Transfer[2] Controller
0025
0026 * An LPC Host Interface Controller manages functions exposed to the host such
0027 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
0028 management and bus snoop configuration.
0029
0030 * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
0031 hardware management protocols for handover between the host and baseboard
0032 management controller.
0033
0034 Additionally the state of the LPC controller influences the pinmux
0035 configuration, therefore the host portion of the controller is exposed as a
0036 syscon as a means to arbitrate access.
0037
0038 properties:
0039 compatible:
0040 items:
0041 - enum:
0042 - aspeed,ast2400-lpc-v2
0043 - aspeed,ast2500-lpc-v2
0044 - aspeed,ast2600-lpc-v2
0045 - const: simple-mfd
0046 - const: syscon
0047
0048 reg:
0049 maxItems: 1
0050
0051 "#address-cells":
0052 const: 1
0053
0054 "#size-cells":
0055 const: 1
0056
0057 ranges: true
0058
0059 patternProperties:
0060 "^lpc-ctrl@[0-9a-f]+$":
0061 type: object
0062 additionalProperties: false
0063
0064 description: |
0065 The LPC Host Interface Controller manages functions exposed to the host such as
0066 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
0067 and bus snoop configuration.
0068
0069 properties:
0070 compatible:
0071 items:
0072 - enum:
0073 - aspeed,ast2400-lpc-ctrl
0074 - aspeed,ast2500-lpc-ctrl
0075 - aspeed,ast2600-lpc-ctrl
0076
0077 reg:
0078 maxItems: 1
0079
0080 clocks:
0081 maxItems: 1
0082
0083 memory-region:
0084 maxItems: 1
0085 description: handle to memory reservation for the LPC to AHB mapping region
0086
0087 flash:
0088 $ref: /schemas/types.yaml#/definitions/phandle
0089 description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
0090
0091 required:
0092 - compatible
0093 - clocks
0094
0095 "^reset-controller@[0-9a-f]+$":
0096 type: object
0097 additionalProperties: false
0098
0099 description:
0100 The UARTs present in the ASPEED SoC can have their resets tied to the reset
0101 state of the LPC bus. Some systems may chose to modify this configuration
0102
0103 properties:
0104 compatible:
0105 items:
0106 - enum:
0107 - aspeed,ast2400-lpc-reset
0108 - aspeed,ast2500-lpc-reset
0109 - aspeed,ast2600-lpc-reset
0110
0111 reg:
0112 maxItems: 1
0113
0114 '#reset-cells':
0115 const: 1
0116
0117 required:
0118 - compatible
0119 - '#reset-cells'
0120
0121 "^lpc-snoop@[0-9a-f]+$":
0122 type: object
0123 additionalProperties: false
0124
0125 description:
0126 The LPC snoop interface allows the BMC to listen on and record the data
0127 bytes written by the Host to the targeted LPC I/O pots.
0128
0129 properties:
0130 compatible:
0131 items:
0132 - enum:
0133 - aspeed,ast2400-lpc-snoop
0134 - aspeed,ast2500-lpc-snoop
0135 - aspeed,ast2600-lpc-snoop
0136
0137 reg:
0138 maxItems: 1
0139
0140 interrupts:
0141 maxItems: 1
0142
0143 snoop-ports:
0144 $ref: /schemas/types.yaml#/definitions/uint32-array
0145 description: The LPC I/O ports to snoop
0146
0147 required:
0148 - compatible
0149 - interrupts
0150 - snoop-ports
0151
0152 "^uart-routing@[0-9a-f]+$":
0153 $ref: /schemas/soc/aspeed/uart-routing.yaml#
0154 description: The UART routing control under LPC register space
0155
0156 required:
0157 - compatible
0158 - reg
0159 - "#address-cells"
0160 - "#size-cells"
0161 - ranges
0162
0163 additionalProperties:
0164 type: object
0165
0166 examples:
0167 - |
0168 #include <dt-bindings/interrupt-controller/arm-gic.h>
0169 #include <dt-bindings/clock/ast2600-clock.h>
0170
0171 lpc: lpc@1e789000 {
0172 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
0173 reg = <0x1e789000 0x1000>;
0174
0175 #address-cells = <1>;
0176 #size-cells = <1>;
0177 ranges = <0x0 0x1e789000 0x1000>;
0178
0179 lpc_ctrl: lpc-ctrl@80 {
0180 compatible = "aspeed,ast2600-lpc-ctrl";
0181 reg = <0x80 0x80>;
0182 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
0183 memory-region = <&flash_memory>;
0184 flash = <&spi>;
0185 };
0186
0187 lpc_reset: reset-controller@98 {
0188 compatible = "aspeed,ast2600-lpc-reset";
0189 reg = <0x98 0x4>;
0190 #reset-cells = <1>;
0191 };
0192
0193 lpc_snoop: lpc-snoop@90 {
0194 compatible = "aspeed,ast2600-lpc-snoop";
0195 reg = <0x90 0x8>;
0196 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0197 snoop-ports = <0x80>;
0198 };
0199 };
