0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A31 PRCM Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 deprecated: true
0014
0015 properties:
0016 compatible:
0017 const: allwinner,sun6i-a31-prcm
0018
0019 reg:
0020 maxItems: 1
0021
0022 patternProperties:
0023 "^.*_(clk|rst)$":
0024 type: object
0025
0026 properties:
0027 compatible:
0028 enum:
0029 - allwinner,sun4i-a10-mod0-clk
0030 - allwinner,sun6i-a31-apb0-clk
0031 - allwinner,sun6i-a31-apb0-gates-clk
0032 - allwinner,sun6i-a31-ar100-clk
0033 - allwinner,sun6i-a31-clock-reset
0034 - fixed-factor-clock
0035
0036 allOf:
0037 - if:
0038 properties:
0039 compatible:
0040 contains:
0041 const: allwinner,sun6i-a31-apb0-clk
0042
0043 then:
0044 properties:
0045 "#clock-cells":
0046 const: 0
0047
0048 # Already checked in the main schema
0049 compatible: true
0050
0051 clocks:
0052 maxItems: 1
0053
0054 clock-output-names:
0055 maxItems: 1
0056
0057 phandle: true
0058
0059 required:
0060 - "#clock-cells"
0061 - compatible
0062 - clocks
0063 - clock-output-names
0064
0065 additionalProperties: false
0066
0067 - if:
0068 properties:
0069 compatible:
0070 contains:
0071 const: allwinner,sun6i-a31-apb0-gates-clk
0072
0073 then:
0074 properties:
0075 "#clock-cells":
0076 const: 1
0077 description: >
0078 This additional argument passed to that clock is the
0079 offset of the bit controlling this particular gate in
0080 the register.
0081
0082 # Already checked in the main schema
0083 compatible: true
0084
0085 clocks:
0086 maxItems: 1
0087
0088 clock-output-names:
0089 minItems: 1
0090 maxItems: 32
0091
0092 phandle: true
0093
0094 required:
0095 - "#clock-cells"
0096 - compatible
0097 - clocks
0098 - clock-output-names
0099
0100 additionalProperties: false
0101
0102 - if:
0103 properties:
0104 compatible:
0105 contains:
0106 const: allwinner,sun6i-a31-ar100-clk
0107
0108 then:
0109 properties:
0110 "#clock-cells":
0111 const: 0
0112
0113 # Already checked in the main schema
0114 compatible: true
0115
0116 clocks:
0117 maxItems: 4
0118 description: >
0119 The parent order must match the hardware programming
0120 order.
0121
0122 clock-output-names:
0123 maxItems: 1
0124
0125 phandle: true
0126
0127 required:
0128 - "#clock-cells"
0129 - compatible
0130 - clocks
0131 - clock-output-names
0132
0133 additionalProperties: false
0134
0135 - if:
0136 properties:
0137 compatible:
0138 contains:
0139 const: allwinner,sun6i-a31-clock-reset
0140
0141 then:
0142 properties:
0143 "#reset-cells":
0144 const: 1
0145
0146 # Already checked in the main schema
0147 compatible: true
0148
0149 phandle: true
0150
0151 required:
0152 - "#reset-cells"
0153 - compatible
0154
0155 additionalProperties: false
0156
0157 required:
0158 - compatible
0159 - reg
0160
0161 additionalProperties: false
0162
0163 examples:
0164 - |
0165 #include <dt-bindings/clock/sun6i-a31-ccu.h>
0166
0167 prcm@1f01400 {
0168 compatible = "allwinner,sun6i-a31-prcm";
0169 reg = <0x01f01400 0x200>;
0170
0171 ar100: ar100_clk {
0172 compatible = "allwinner,sun6i-a31-ar100-clk";
0173 #clock-cells = <0>;
0174 clocks = <&rtc 0>, <&osc24M>,
0175 <&ccu CLK_PLL_PERIPH>,
0176 <&ccu CLK_PLL_PERIPH>;
0177 clock-output-names = "ar100";
0178 };
0179
0180 ahb0: ahb0_clk {
0181 compatible = "fixed-factor-clock";
0182 #clock-cells = <0>;
0183 clock-div = <1>;
0184 clock-mult = <1>;
0185 clocks = <&ar100>;
0186 clock-output-names = "ahb0";
0187 };
0188
0189 apb0: apb0_clk {
0190 compatible = "allwinner,sun6i-a31-apb0-clk";
0191 #clock-cells = <0>;
0192 clocks = <&ahb0>;
0193 clock-output-names = "apb0";
0194 };
0195
0196 apb0_gates: apb0_gates_clk {
0197 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
0198 #clock-cells = <1>;
0199 clocks = <&apb0>;
0200 clock-output-names = "apb0_pio", "apb0_ir",
0201 "apb0_timer", "apb0_p2wi",
0202 "apb0_uart", "apb0_1wire",
0203 "apb0_i2c";
0204 };
0205
0206 ir_clk: ir_clk {
0207 #clock-cells = <0>;
0208 compatible = "allwinner,sun4i-a10-mod0-clk";
0209 clocks = <&rtc 0>, <&osc24M>;
0210 clock-output-names = "ir";
0211 };
0212
0213 apb0_rst: apb0_rst {
0214 compatible = "allwinner,sun6i-a31-clock-reset";
0215 #reset-cells = <1>;
0216 };
0217 };
0218
0219 ...
