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0001 * Device tree bindings for Texas instruments AEMIF controller
0002 
0003 The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
0004 provide a glue-less interface to a variety of asynchronous memory devices like
0005 ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
0006 can be accessed at any given time via four chip selects with 64M byte access
0007 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
0008 and Mobile SDR are not supported.
0009 
0010 Documentation:
0011 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
0012 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
0013 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
0014 
0015 Required properties:
0016 
0017 - compatible:           "ti,davinci-aemif"
0018                         "ti,keystone-aemif"
0019                         "ti,da850-aemif"
0020 
0021 - reg:                  contains offset/length value for AEMIF control registers
0022                         space.
0023 
0024 - #address-cells:       Must be 2. The partition number has to be encoded in the
0025                         first address cell and it may accept values 0..N-1
0026                         (N - total number of partitions). It's recommended to
0027                         assign N-1 number for the control partition. The second
0028                         cell is the offset into the partition.
0029 
0030 - #size-cells:          Must be set to 1.
0031 
0032 - ranges:               Contains memory regions. There are two types of
0033                         ranges/partitions:
0034                         - CS-specific partition/range. If continuous, must be
0035                         set up to reflect the memory layout for 4 chipselects,
0036                         if not then additional range/partition can be added and
0037                         child device can select the proper one.
0038                         - control partition which is common for all CS
0039                         interfaces.
0040 
0041 - clocks:               the clock feeding the controller clock. Required only
0042                         if clock tree data present in device tree.
0043                         See clock-bindings.txt
0044 
0045 - clock-names:          clock name. It has to be "aemif". Required only if clock
0046                         tree data present in device tree, in another case don't
0047                         use it.
0048                         See clock-bindings.txt
0049 
0050 - clock-ranges:         Empty property indicating that child nodes can inherit
0051                         named clocks. Required only if clock tree data present
0052                         in device tree.
0053                         See clock-bindings.txt
0054 
0055 
0056 Child chip-select (cs) nodes contain the memory devices nodes connected to
0057 such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
0058 There might be board specific devices like FPGAs.
0059 
0060 Required child cs node properties:
0061 
0062 - #address-cells:       Must be 2.
0063 
0064 - #size-cells:          Must be 1.
0065 
0066 - ranges:               Empty property indicating that child nodes can inherit
0067                         memory layout.
0068 
0069 - clock-ranges:         Empty property indicating that child nodes can inherit
0070                         named clocks. Required only if clock tree data present
0071                         in device tree.
0072 
0073 - ti,cs-chipselect:     number of chipselect. Indicates on the aemif driver
0074                         which chipselect is used for accessing the memory. For
0075                         compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
0076                         it can be in range [0-3]. For compatible
0077                         "ti,da850-aemif" range is [2-5].
0078 
0079 Optional child cs node properties:
0080 
0081 - ti,cs-bus-width:              width of the asynchronous device's data bus
0082                                 8 or 16 if not preset 8
0083 
0084 - ti,cs-select-strobe-mode:     enable/disable select strobe mode
0085                                 In select strobe mode chip select behaves as
0086                                 the strobe and is active only during the strobe
0087                                 period. If present then enable.
0088 
0089 - ti,cs-extended-wait-mode:     enable/disable extended wait mode
0090                                 if set, the controller monitors the EMIFWAIT pin
0091                                 mapped to that chip select to determine if the
0092                                 device wants to extend the strobe period. If
0093                                 present then enable.
0094 
0095 - ti,cs-min-turnaround-ns:      minimum turn around time, ns
0096                                 Time between the end of one asynchronous memory
0097                                 access and the start of another asynchronous
0098                                 memory access. This delay is not incurred
0099                                 between a read followed by read or a write
0100                                 followed by a write to same chip select.
0101 
0102 - ti,cs-read-setup-ns:          read setup width, ns
0103                                 Time between the beginning of a memory cycle
0104                                 and the activation of read strobe.
0105                                 Minimum value is 1 (0 treated as 1).
0106 
0107 - ti,cs-read-strobe-ns:         read strobe width, ns
0108                                 Time between the activation and deactivation of
0109                                 the read strobe.
0110                                 Minimum value is 1 (0 treated as 1).
0111 
0112 - ti,cs-read-hold-ns:           read hold width, ns
0113                                 Time between the deactivation of the read
0114                                 strobe and the end of the cycle (which may be
0115                                 either an address change or the deactivation of
0116                                 the chip select signal.
0117                                 Minimum value is 1 (0 treated as 1).
0118 
0119 - ti,cs-write-setup-ns:         write setup width, ns
0120                                 Time between the beginning of a memory cycle
0121                                 and the activation of write strobe.
0122                                 Minimum value is 1 (0 treated as 1).
0123 
0124 - ti,cs-write-strobe-ns:        write strobe width, ns
0125                                 Time between the activation and deactivation of
0126                                 the write strobe.
0127                                 Minimum value is 1 (0 treated as 1).
0128 
0129 - ti,cs-write-hold-ns:          write hold width, ns
0130                                 Time between the deactivation of the write
0131                                 strobe and the end of the cycle (which may be
0132                                 either an address change or the deactivation of
0133                                 the chip select signal.
0134                                 Minimum value is 1 (0 treated as 1).
0135 
0136 If any of the above parameters are absent, current parameter value will be taken
0137 from the corresponding HW reg.
0138 
0139 Example for aemif, davinci nand and nor flash chip select shown below.
0140 
0141 memory-controller@21000a00 {
0142         compatible = "ti,davinci-aemif";
0143         #address-cells = <2>;
0144         #size-cells = <1>;
0145         clocks = <&clkaemif 0>;
0146         clock-names = "aemif";
0147         clock-ranges;
0148         reg = <0x21000A00 0x00000100>;
0149         ranges = <0 0 0x70000000 0x10000000
0150                   1 0 0x21000A00 0x00000100>;
0151                   /*
0152                    * Partition0: CS-specific memory range which is
0153                    * implemented as continuous physical memory region
0154                    * Partition1: control memory range
0155                    */
0156 
0157         nand:cs2 {
0158                 #address-cells = <2>;
0159                 #size-cells = <1>;
0160                 clock-ranges;
0161                 ranges;
0162 
0163                 ti,cs-chipselect = <2>;
0164                 /* all timings in nanoseconds */
0165                 ti,cs-min-turnaround-ns = <0>;
0166                 ti,cs-read-hold-ns = <7>;
0167                 ti,cs-read-strobe-ns = <42>;
0168                 ti,cs-read-setup-ns = <14>;
0169                 ti,cs-write-hold-ns = <7>;
0170                 ti,cs-write-strobe-ns = <42>;
0171                 ti,cs-write-setup-ns = <14>;
0172 
0173                 nand@0,0x8000000 {
0174                         compatible = "ti,davinci-nand";
0175                         reg = <0 0x8000000 0x4000000
0176                                1 0x0000000 0x0000100>;
0177                         /*
0178                          * Partition0, offset 0x8000000, size 0x4000000
0179                          * Partition1, offset 0x0000000, size 0x0000100
0180                          */
0181 
0182                         .. see davinci-nand.txt
0183                 };
0184         };
0185 
0186         nor:cs0 {
0187                 #address-cells = <2>;
0188                 #size-cells = <1>;
0189                 clock-ranges;
0190                 ranges;
0191 
0192                 ti,cs-chipselect = <0>;
0193                 /* all timings in nanoseconds */
0194                 ti,cs-min-turnaround-ns = <0>;
0195                 ti,cs-read-hold-ns = <8>;
0196                 ti,cs-read-strobe-ns = <40>;
0197                 ti,cs-read-setup-ns = <14>;
0198                 ti,cs-write-hold-ns = <7>;
0199                 ti,cs-write-strobe-ns = <40>;
0200                 ti,cs-write-setup-ns = <14>;
0201                 ti,cs-bus-width = <16>;
0202 
0203                 flash@0,0x0000000 {
0204                         compatible = "cfi-flash";
0205                         reg = <0 0x0000000 0x4000000>;
0206 
0207                         ...
0208                 };
0209         };
0210 };