0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments GPMC Memory Controller device-tree bindings
0008
0009 maintainers:
0010 - Tony Lindgren <tony@atomide.com>
0011 - Roger Quadros <rogerq@kernel.org>
0012
0013 description:
0014 The GPMC is a unified memory controller dedicated for interfacing
0015 with external memory devices like
0016 - Asynchronous SRAM-like memories and ASICs
0017 - Asynchronous, synchronous, and page mode burst NOR flash
0018 - NAND flash
0019 - Pseudo-SRAM devices
0020
0021 properties:
0022 compatible:
0023 items:
0024 - enum:
0025 - ti,am3352-gpmc
0026 - ti,am64-gpmc
0027 - ti,omap2420-gpmc
0028 - ti,omap2430-gpmc
0029 - ti,omap3430-gpmc
0030 - ti,omap4430-gpmc
0031
0032 reg:
0033 minItems: 1
0034 maxItems: 2
0035
0036 reg-names:
0037 items:
0038 - const: cfg
0039 - const: data
0040
0041 interrupts:
0042 maxItems: 1
0043
0044 clocks:
0045 maxItems: 1
0046 description: |
0047 Functional clock. Used for bus timing calculations and
0048 GPMC configuration.
0049
0050 clock-names:
0051 items:
0052 - const: fck
0053
0054 power-domains:
0055 maxItems: 1
0056
0057 dmas:
0058 items:
0059 - description: DMA channel for GPMC NAND prefetch
0060
0061 dma-names:
0062 items:
0063 - const: rxtx
0064
0065 "#address-cells": true
0066
0067 "#size-cells": true
0068
0069 gpmc,num-cs:
0070 description: maximum number of supported chip-select lines.
0071 $ref: /schemas/types.yaml#/definitions/uint32
0072
0073 gpmc,num-waitpins:
0074 description: maximum number of supported wait pins.
0075 $ref: /schemas/types.yaml#/definitions/uint32
0076
0077 ranges:
0078 minItems: 1
0079 description: |
0080 Must be set up to reflect the memory layout with four
0081 integer values for each chip-select line in use,
0082 <cs-number> 0 <physical address of mapping> <size>
0083 items:
0084 - description: NAND bank 0
0085 - description: NOR/SRAM bank 0
0086 - description: NOR/SRAM bank 1
0087
0088 '#interrupt-cells':
0089 const: 2
0090
0091 interrupt-controller:
0092 description: |
0093 The GPMC driver implements and interrupt controller for
0094 the NAND events "fifoevent" and "termcount" plus the
0095 rising/falling edges on the GPMC_WAIT pins.
0096 The interrupt number mapping is as follows
0097 0 - NAND_fifoevent
0098 1 - NAND_termcount
0099 2 - GPMC_WAIT0 pin edge
0100 3 - GPMC_WAIT1 pin edge, and so on.
0101
0102 '#gpio-cells':
0103 const: 2
0104
0105 gpio-controller:
0106 description: |
0107 The GPMC driver implements a GPIO controller for the
0108 GPMC WAIT pins that can be used as general purpose inputs.
0109 0 maps to GPMC_WAIT0 pin.
0110
0111 ti,hwmods:
0112 description:
0113 Name of the HWMOD associated with GPMC. This is for legacy
0114 omap2/3 platforms only.
0115 $ref: /schemas/types.yaml#/definitions/string
0116 deprecated: true
0117
0118 ti,no-idle-on-init:
0119 description:
0120 Prevent idling the module at init. This is for legacy omap2/3
0121 platforms only.
0122 type: boolean
0123 deprecated: true
0124
0125 patternProperties:
0126 "@[0-7],[a-f0-9]+$":
0127 type: object
0128 description: |
0129 The child device node represents the device connected to the GPMC
0130 bus. The device can be a NAND chip, SRAM device, NOR device
0131 or an ASIC.
0132 $ref: "ti,gpmc-child.yaml"
0133
0134
0135 required:
0136 - compatible
0137 - reg
0138 - gpmc,num-cs
0139 - gpmc,num-waitpins
0140 - "#address-cells"
0141 - "#size-cells"
0142
0143 allOf:
0144 - if:
0145 properties:
0146 compatible:
0147 contains:
0148 const: ti,am64-gpmc
0149 then:
0150 required:
0151 - reg-names
0152 - power-domains
0153
0154 additionalProperties: false
0155
0156 examples:
0157 - |
0158 #include <dt-bindings/interrupt-controller/arm-gic.h>
0159 #include <dt-bindings/gpio/gpio.h>
0160
0161 gpmc: memory-controller@50000000 {
0162 compatible = "ti,am3352-gpmc";
0163 reg = <0x50000000 0x2000>;
0164 interrupts = <100>;
0165 clocks = <&l3s_clkctrl>;
0166 clock-names = "fck";
0167 dmas = <&edma 52 0>;
0168 dma-names = "rxtx";
0169 gpmc,num-cs = <8>;
0170 gpmc,num-waitpins = <2>;
0171 #address-cells = <2>;
0172 #size-cells = <1>;
0173 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
0174 interrupt-controller;
0175 #interrupt-cells = <2>;
0176 gpio-controller;
0177 #gpio-cells = <2>;
0178
0179 nand@0,0 {
0180 compatible = "ti,omap2-nand";
0181 reg = <0 0 4>;
0182 interrupt-parent = <&gpmc>;
0183 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
0184 <1 IRQ_TYPE_NONE>; /* termcount */
0185 ti,nand-xfer-type = "prefetch-dma";
0186 ti,nand-ecc-opt = "bch16";
0187 ti,elm-id = <&elm>;
0188 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
0189 };
0190 };
