0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Synopsys IntelliDDR Multi Protocol memory controller
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011 - Manish Narani <manish.narani@xilinx.com>
0012 - Michal Simek <michal.simek@xilinx.com>
0013
0014 description: |
0015 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
0016 32-bit bus width configurations.
0017
0018 The Zynq DDR ECC controller has an optional ECC support in half-bus width
0019 (16-bit) configuration.
0020
0021 These both ECC controllers correct single bit ECC errors and detect double bit
0022 ECC errors.
0023
0024 properties:
0025 compatible:
0026 enum:
0027 - snps,ddrc-3.80a
0028 - xlnx,zynq-ddrc-a05
0029 - xlnx,zynqmp-ddrc-2.40a
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 reg:
0035 maxItems: 1
0036
0037 required:
0038 - compatible
0039 - reg
0040
0041 allOf:
0042 - if:
0043 properties:
0044 compatible:
0045 contains:
0046 enum:
0047 - snps,ddrc-3.80a
0048 - xlnx,zynqmp-ddrc-2.40a
0049 then:
0050 required:
0051 - interrupts
0052 else:
0053 properties:
0054 interrupts: false
0055
0056 additionalProperties: false
0057
0058 examples:
0059 - |
0060 memory-controller@f8006000 {
0061 compatible = "xlnx,zynq-ddrc-a05";
0062 reg = <0xf8006000 0x1000>;
0063 };
0064
0065 - |
0066 axi {
0067 #address-cells = <2>;
0068 #size-cells = <2>;
0069
0070 memory-controller@fd070000 {
0071 compatible = "xlnx,zynqmp-ddrc-2.40a";
0072 reg = <0x0 0xfd070000 0x0 0x30000>;
0073 interrupt-parent = <&gic>;
0074 interrupts = <0 112 4>;
0075 };
0076 };
