0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
0008
0009 description: |
0010 The FMC2 functional block makes the interface with: synchronous and
0011 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
0012 peripherals) and NAND flash memories.
0013 Its main purposes are:
0014 - to translate AXI transactions into the appropriate external device
0015 protocol
0016 - to meet the access time requirements of the external devices
0017 All external devices share the addresses, data and control signals with the
0018 controller. Each external device is accessed by means of a unique Chip
0019 Select. The FMC2 performs only one access at a time to an external device.
0020
0021 maintainers:
0022 - Christophe Kerello <christophe.kerello@foss.st.com>
0023
0024 properties:
0025 compatible:
0026 const: st,stm32mp1-fmc2-ebi
0027
0028 reg:
0029 maxItems: 1
0030
0031 clocks:
0032 maxItems: 1
0033
0034 resets:
0035 maxItems: 1
0036
0037 "#address-cells":
0038 const: 2
0039
0040 "#size-cells":
0041 const: 1
0042
0043 ranges:
0044 description: |
0045 Reflects the memory layout with four integer values per bank. Format:
0046 <bank-number> 0 <address of the bank> <size>
0047
0048 patternProperties:
0049 "^.*@[0-4],[a-f0-9]+$":
0050 type: object
0051
0052 properties:
0053 reg:
0054 description: Bank number, base address and size of the device.
0055
0056 st,fmc2-ebi-cs-transaction-type:
0057 description: |
0058 Select one of the transactions type supported
0059 0: Asynchronous mode 1 SRAM/FRAM.
0060 1: Asynchronous mode 1 PSRAM.
0061 2: Asynchronous mode A SRAM/FRAM.
0062 3: Asynchronous mode A PSRAM.
0063 4: Asynchronous mode 2 NOR.
0064 5: Asynchronous mode B NOR.
0065 6: Asynchronous mode C NOR.
0066 7: Asynchronous mode D NOR.
0067 8: Synchronous read synchronous write PSRAM.
0068 9: Synchronous read asynchronous write PSRAM.
0069 10: Synchronous read synchronous write NOR.
0070 11: Synchronous read asynchronous write NOR.
0071 $ref: /schemas/types.yaml#/definitions/uint32
0072 minimum: 0
0073 maximum: 11
0074
0075 st,fmc2-ebi-cs-cclk-enable:
0076 description: Continuous clock enable (first bank must be configured
0077 in synchronous mode). The FMC_CLK is generated continuously
0078 during asynchronous and synchronous access. By default, the
0079 FMC_CLK is only generated during synchronous access.
0080 $ref: /schemas/types.yaml#/definitions/flag
0081
0082 st,fmc2-ebi-cs-mux-enable:
0083 description: Address/Data multiplexed on databus (valid only with
0084 NOR and PSRAM transactions type). By default, Address/Data
0085 are not multiplexed.
0086 $ref: /schemas/types.yaml#/definitions/flag
0087
0088 st,fmc2-ebi-cs-buswidth:
0089 description: Data bus width
0090 $ref: /schemas/types.yaml#/definitions/uint32
0091 enum: [ 8, 16 ]
0092 default: 16
0093
0094 st,fmc2-ebi-cs-waitpol-high:
0095 description: Wait signal polarity (NWAIT signal active high).
0096 By default, NWAIT is active low.
0097 $ref: /schemas/types.yaml#/definitions/flag
0098
0099 st,fmc2-ebi-cs-waitcfg-enable:
0100 description: The NWAIT signal indicates wheither the data from the
0101 device are valid or if a wait state must be inserted when accessing
0102 the device in synchronous mode. By default, the NWAIT signal is
0103 active one data cycle before wait state.
0104 $ref: /schemas/types.yaml#/definitions/flag
0105
0106 st,fmc2-ebi-cs-wait-enable:
0107 description: The NWAIT signal is enabled (its level is taken into
0108 account after the programmed latency period to insert wait states
0109 if asserted). By default, the NWAIT signal is disabled.
0110 $ref: /schemas/types.yaml#/definitions/flag
0111
0112 st,fmc2-ebi-cs-asyncwait-enable:
0113 description: The NWAIT signal is taken into account during asynchronous
0114 transactions. By default, the NWAIT signal is not taken into account
0115 during asynchronous transactions.
0116 $ref: /schemas/types.yaml#/definitions/flag
0117
0118 st,fmc2-ebi-cs-cpsize:
0119 description: CRAM page size. The controller splits the burst access
0120 when the memory page is reached. By default, no burst split when
0121 crossing page boundary.
0122 $ref: /schemas/types.yaml#/definitions/uint32
0123 enum: [ 0, 128, 256, 512, 1024 ]
0124 default: 0
0125
0126 st,fmc2-ebi-cs-byte-lane-setup-ns:
0127 description: This property configures the byte lane setup timing
0128 defined in nanoseconds from NBLx low to Chip Select NEx low.
0129
0130 st,fmc2-ebi-cs-address-setup-ns:
0131 description: This property defines the duration of the address setup
0132 phase in nanoseconds used for asynchronous read/write transactions.
0133
0134 st,fmc2-ebi-cs-address-hold-ns:
0135 description: This property defines the duration of the address hold
0136 phase in nanoseconds used for asynchronous multiplexed read/write
0137 transactions.
0138
0139 st,fmc2-ebi-cs-data-setup-ns:
0140 description: This property defines the duration of the data setup phase
0141 in nanoseconds used for asynchronous read/write transactions.
0142
0143 st,fmc2-ebi-cs-bus-turnaround-ns:
0144 description: This property defines the delay in nanoseconds between the
0145 end of current read/write transaction and the next transaction.
0146
0147 st,fmc2-ebi-cs-data-hold-ns:
0148 description: This property defines the duration of the data hold phase
0149 in nanoseconds used for asynchronous read/write transactions.
0150
0151 st,fmc2-ebi-cs-clk-period-ns:
0152 description: This property defines the FMC_CLK output signal period in
0153 nanoseconds.
0154
0155 st,fmc2-ebi-cs-data-latency-ns:
0156 description: This property defines the data latency before reading or
0157 writing the first data in nanoseconds.
0158
0159 st,fmc2_ebi-cs-write-address-setup-ns:
0160 description: This property defines the duration of the address setup
0161 phase in nanoseconds used for asynchronous write transactions.
0162
0163 st,fmc2-ebi-cs-write-address-hold-ns:
0164 description: This property defines the duration of the address hold
0165 phase in nanoseconds used for asynchronous multiplexed write
0166 transactions.
0167
0168 st,fmc2-ebi-cs-write-data-setup-ns:
0169 description: This property defines the duration of the data setup
0170 phase in nanoseconds used for asynchronous write transactions.
0171
0172 st,fmc2-ebi-cs-write-bus-turnaround-ns:
0173 description: This property defines the delay between the end of current
0174 write transaction and the next transaction in nanoseconds.
0175
0176 st,fmc2-ebi-cs-write-data-hold-ns:
0177 description: This property defines the duration of the data hold phase
0178 in nanoseconds used for asynchronous write transactions.
0179
0180 st,fmc2-ebi-cs-max-low-pulse-ns:
0181 description: This property defines the maximum chip select low pulse
0182 duration in nanoseconds for synchronous transactions. When this timing
0183 reaches 0, the controller splits the current access, toggles NE to
0184 allow device refresh and restarts a new access.
0185
0186 required:
0187 - reg
0188
0189 required:
0190 - "#address-cells"
0191 - "#size-cells"
0192 - compatible
0193 - reg
0194 - clocks
0195 - ranges
0196
0197 additionalProperties: false
0198
0199 examples:
0200 - |
0201 #include <dt-bindings/interrupt-controller/arm-gic.h>
0202 #include <dt-bindings/clock/stm32mp1-clks.h>
0203 #include <dt-bindings/reset/stm32mp1-resets.h>
0204 memory-controller@58002000 {
0205 #address-cells = <2>;
0206 #size-cells = <1>;
0207 compatible = "st,stm32mp1-fmc2-ebi";
0208 reg = <0x58002000 0x1000>;
0209 clocks = <&rcc FMC_K>;
0210 resets = <&rcc FMC_R>;
0211
0212 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
0213 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
0214 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
0215 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
0216 <4 0 0x80000000 0x10000000>; /* NAND */
0217
0218 psram@0,0 {
0219 compatible = "mtd-ram";
0220 reg = <0 0x00000000 0x100000>;
0221 bank-width = <2>;
0222
0223 st,fmc2-ebi-cs-transaction-type = <1>;
0224 st,fmc2-ebi-cs-address-setup-ns = <60>;
0225 st,fmc2-ebi-cs-data-setup-ns = <30>;
0226 st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
0227 };
0228
0229 nand-controller@4,0 {
0230 #address-cells = <1>;
0231 #size-cells = <0>;
0232 compatible = "st,stm32mp1-fmc2-nfc";
0233 reg = <4 0x00000000 0x1000>,
0234 <4 0x08010000 0x1000>,
0235 <4 0x08020000 0x1000>,
0236 <4 0x01000000 0x1000>,
0237 <4 0x09010000 0x1000>,
0238 <4 0x09020000 0x1000>;
0239 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0240 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
0241 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
0242 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
0243 dma-names = "tx", "rx", "ecc";
0244
0245 nand@0 {
0246 reg = <0>;
0247 nand-on-flash-bbt;
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 };
0251 };
0252 };
0253
0254 ...
