0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: |
0008 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
0009 Controller device
0010
0011 maintainers:
0012 - Krzysztof Kozlowski <krzk@kernel.org>
0013 - Lukasz Luba <lukasz.luba@arm.com>
0014
0015 description: |
0016 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
0017 DRAM memory chips are connected. The driver is to monitor the controller in
0018 runtime and switch frequency and voltage. To monitor the usage of the
0019 controller in runtime, the driver uses the PPMU (Platform Performance
0020 Monitoring Unit), which is able to measure the current load of the memory.
0021 When 'userspace' governor is used for the driver, an application is able to
0022 switch the DMC and memory frequency.
0023
0024 properties:
0025 compatible:
0026 items:
0027 - const: samsung,exynos5422-dmc
0028
0029 clock-names:
0030 items:
0031 - const: fout_spll
0032 - const: mout_sclk_spll
0033 - const: ff_dout_spll2
0034 - const: fout_bpll
0035 - const: mout_bpll
0036 - const: sclk_bpll
0037 - const: mout_mx_mspll_ccore
0038 - const: mout_mclk_cdrex
0039
0040 clocks:
0041 minItems: 8
0042 maxItems: 8
0043
0044 devfreq-events:
0045 $ref: '/schemas/types.yaml#/definitions/phandle-array'
0046 minItems: 1
0047 maxItems: 16
0048 items:
0049 maxItems: 1
0050 description: phandles of the PPMU events used by the controller.
0051
0052 device-handle:
0053 $ref: '/schemas/types.yaml#/definitions/phandle'
0054 description: |
0055 phandle of the connected DRAM memory device. For more information please
0056 refer to jedec,lpddr3.yaml.
0057
0058 operating-points-v2: true
0059
0060 interrupts:
0061 items:
0062 - description: DMC internal performance event counters in DREX0
0063 - description: DMC internal performance event counters in DREX1
0064
0065 interrupt-names:
0066 items:
0067 - const: drex_0
0068 - const: drex_1
0069
0070 reg:
0071 items:
0072 - description: registers of DREX0
0073 - description: registers of DREX1
0074
0075 samsung,syscon-clk:
0076 $ref: '/schemas/types.yaml#/definitions/phandle'
0077 description: |
0078 Phandle of the clock register set used by the controller, these registers
0079 are used for enabling a 'pause' feature and are not exposed by clock
0080 framework but they must be used in a safe way. The register offsets are
0081 in the driver code and specyfic for this SoC type.
0082
0083 vdd-supply: true
0084
0085 required:
0086 - compatible
0087 - clock-names
0088 - clocks
0089 - devfreq-events
0090 - device-handle
0091 - reg
0092 - samsung,syscon-clk
0093
0094 additionalProperties: false
0095
0096 examples:
0097 - |
0098 #include <dt-bindings/clock/exynos5420.h>
0099 ppmu_dmc0_0: ppmu@10d00000 {
0100 compatible = "samsung,exynos-ppmu";
0101 reg = <0x10d00000 0x2000>;
0102 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
0103 clock-names = "ppmu";
0104 events {
0105 ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
0106 event-name = "ppmu-event3-dmc0_0";
0107 };
0108 };
0109 };
0110
0111 memory-controller@10c20000 {
0112 compatible = "samsung,exynos5422-dmc";
0113 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
0114 clocks = <&clock CLK_FOUT_SPLL>,
0115 <&clock CLK_MOUT_SCLK_SPLL>,
0116 <&clock CLK_FF_DOUT_SPLL2>,
0117 <&clock CLK_FOUT_BPLL>,
0118 <&clock CLK_MOUT_BPLL>,
0119 <&clock CLK_SCLK_BPLL>,
0120 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
0121 <&clock CLK_MOUT_MCLK_CDREX>;
0122 clock-names = "fout_spll",
0123 "mout_sclk_spll",
0124 "ff_dout_spll2",
0125 "fout_bpll",
0126 "mout_bpll",
0127 "sclk_bpll",
0128 "mout_mx_mspll_ccore",
0129 "mout_mclk_cdrex";
0130 operating-points-v2 = <&dmc_opp_table>;
0131 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
0132 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
0133 device-handle = <&samsung_K3QF2F20DB>;
0134 vdd-supply = <&buck1_reg>;
0135 samsung,syscon-clk = <&clock>;
0136 interrupt-parent = <&combiner>;
0137 interrupts = <16 0>, <16 1>;
0138 interrupt-names = "drex_0", "drex_1";
0139 };
