0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
0008
0009 maintainers:
0010 - Brian Norris <briannorris@chromium.org>
0011
0012 properties:
0013 compatible:
0014 enum:
0015 - rockchip,rk3399-dmc
0016
0017 devfreq-events:
0018 $ref: /schemas/types.yaml#/definitions/phandle
0019 description:
0020 Node to get DDR loading. Refer to
0021 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
0022
0023 clocks:
0024 maxItems: 1
0025
0026 clock-names:
0027 items:
0028 - const: dmc_clk
0029
0030 operating-points-v2: true
0031
0032 center-supply:
0033 description:
0034 DMC regulator supply.
0035
0036 rockchip,pmu:
0037 $ref: /schemas/types.yaml#/definitions/phandle
0038 description:
0039 Phandle to the syscon managing the "PMU general register files".
0040
0041 interrupts:
0042 maxItems: 1
0043 description:
0044 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
0045 finishes, a DCF interrupt is triggered.
0046
0047 rockchip,ddr3_speed_bin:
0048 deprecated: true
0049 $ref: /schemas/types.yaml#/definitions/uint32
0050 description:
0051 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
0052 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
0053 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
0054 being used.
0055
0056 rockchip,pd_idle:
0057 deprecated: true
0058 $ref: /schemas/types.yaml#/definitions/uint32
0059 description:
0060 Configure the PD_IDLE value. Defines the power-down idle period in which
0061 memories are placed into power-down mode if bus is idle for PD_IDLE DFI
0062 clock cycles.
0063 See also rockchip,pd-idle-ns.
0064
0065 rockchip,sr_idle:
0066 deprecated: true
0067 $ref: /schemas/types.yaml#/definitions/uint32
0068 description:
0069 Configure the SR_IDLE value. Defines the self-refresh idle period in
0070 which memories are placed into self-refresh mode if bus is idle for
0071 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
0072 See also rockchip,sr-idle-ns.
0073 default: 0
0074
0075 rockchip,sr_mc_gate_idle:
0076 deprecated: true
0077 $ref: /schemas/types.yaml#/definitions/uint32
0078 description:
0079 Defines the memory self-refresh and controller clock gating idle period.
0080 Memories are placed into self-refresh mode and memory controller clock
0081 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
0082 cycles.
0083 See also rockchip,sr-mc-gate-idle-ns.
0084
0085 rockchip,srpd_lite_idle:
0086 deprecated: true
0087 $ref: /schemas/types.yaml#/definitions/uint32
0088 description:
0089 Defines the self-refresh power down idle period in which memories are
0090 placed into self-refresh power down mode if bus is idle for
0091 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
0092 only.
0093 See also rockchip,srpd-lite-idle-ns.
0094
0095 rockchip,standby_idle:
0096 deprecated: true
0097 $ref: /schemas/types.yaml#/definitions/uint32
0098 description:
0099 Defines the standby idle period in which memories are placed into
0100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
0101 if bus is idle for standby_idle * DFI clock cycles.
0102 See also rockchip,standby-idle-ns.
0103
0104 rockchip,dram_dll_dis_freq:
0105 deprecated: true
0106 $ref: /schemas/types.yaml#/definitions/uint32
0107 description: |
0108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
0109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
0110 Note: if DLL was bypassed, the odt will also stop working.
0111
0112 rockchip,phy_dll_dis_freq:
0113 deprecated: true
0114 $ref: /schemas/types.yaml#/definitions/uint32
0115 description: |
0116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
0117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
0118 Note: PHY DLL and PHY ODT are independent.
0119
0120 rockchip,auto_pd_dis_freq:
0121 deprecated: true
0122 $ref: /schemas/types.yaml#/definitions/uint32
0123 description:
0124 Defines the auto PD disable frequency in MHz.
0125
0126 rockchip,ddr3_odt_dis_freq:
0127 $ref: /schemas/types.yaml#/definitions/uint32
0128 minimum: 1000000 # In case anyone thought this was MHz.
0129 description:
0130 When the DRAM type is DDR3, this parameter defines the ODT disable
0131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
0132 the ODT on the DRAM side and controller side are both disabled.
0133
0134 rockchip,ddr3_drv:
0135 deprecated: true
0136 $ref: /schemas/types.yaml#/definitions/uint32
0137 description:
0138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
0139 strength in ohms.
0140 default: 40
0141
0142 rockchip,ddr3_odt:
0143 deprecated: true
0144 $ref: /schemas/types.yaml#/definitions/uint32
0145 description:
0146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
0147 strength in ohms.
0148 default: 120
0149
0150 rockchip,phy_ddr3_ca_drv:
0151 deprecated: true
0152 $ref: /schemas/types.yaml#/definitions/uint32
0153 description:
0154 When the DRAM type is DDR3, this parameter defines the phy side CA line
0155 (incluing command line, address line and clock line) drive strength.
0156 default: 40
0157
0158 rockchip,phy_ddr3_dq_drv:
0159 deprecated: true
0160 $ref: /schemas/types.yaml#/definitions/uint32
0161 description:
0162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
0163 (including DQS/DQ/DM line) drive strength.
0164 default: 40
0165
0166 rockchip,phy_ddr3_odt:
0167 deprecated: true
0168 $ref: /schemas/types.yaml#/definitions/uint32
0169 description:
0170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
0171 strength.
0172 default: 240
0173
0174 rockchip,lpddr3_odt_dis_freq:
0175 $ref: /schemas/types.yaml#/definitions/uint32
0176 minimum: 1000000 # In case anyone thought this was MHz.
0177 description:
0178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
0179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
0180 ODT on the DRAM side and controller side are both disabled.
0181
0182 rockchip,lpddr3_drv:
0183 deprecated: true
0184 $ref: /schemas/types.yaml#/definitions/uint32
0185 description:
0186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
0187 strength in ohms.
0188 default: 34
0189
0190 rockchip,lpddr3_odt:
0191 deprecated: true
0192 $ref: /schemas/types.yaml#/definitions/uint32
0193 description:
0194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
0195 strength in ohms.
0196 default: 240
0197
0198 rockchip,phy_lpddr3_ca_drv:
0199 deprecated: true
0200 $ref: /schemas/types.yaml#/definitions/uint32
0201 description:
0202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
0203 (including command line, address line and clock line) drive strength.
0204 default: 40
0205
0206 rockchip,phy_lpddr3_dq_drv:
0207 deprecated: true
0208 $ref: /schemas/types.yaml#/definitions/uint32
0209 description:
0210 When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
0211 (including DQS/DQ/DM line) drive strength.
0212 default: 40
0213
0214 rockchip,phy_lpddr3_odt:
0215 deprecated: true
0216 $ref: /schemas/types.yaml#/definitions/uint32
0217 description:
0218 When dram type is LPDDR3, this parameter define the phy side odt
0219 strength, default value is 240.
0220
0221 rockchip,lpddr4_odt_dis_freq:
0222 $ref: /schemas/types.yaml#/definitions/uint32
0223 minimum: 1000000 # In case anyone thought this was MHz.
0224 description:
0225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
0226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
0227 the ODT on the DRAM side and controller side are both disabled.
0228
0229 rockchip,lpddr4_drv:
0230 deprecated: true
0231 $ref: /schemas/types.yaml#/definitions/uint32
0232 description:
0233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
0234 strength in ohms.
0235 default: 60
0236
0237 rockchip,lpddr4_dq_odt:
0238 deprecated: true
0239 $ref: /schemas/types.yaml#/definitions/uint32
0240 description:
0241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
0242 DQS/DQ line strength in ohms.
0243 default: 40
0244
0245 rockchip,lpddr4_ca_odt:
0246 deprecated: true
0247 $ref: /schemas/types.yaml#/definitions/uint32
0248 description:
0249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
0250 CA line strength in ohms.
0251 default: 40
0252
0253 rockchip,phy_lpddr4_ca_drv:
0254 deprecated: true
0255 $ref: /schemas/types.yaml#/definitions/uint32
0256 description:
0257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
0258 (including command address line) drive strength.
0259 default: 40
0260
0261 rockchip,phy_lpddr4_ck_cs_drv:
0262 deprecated: true
0263 $ref: /schemas/types.yaml#/definitions/uint32
0264 description:
0265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
0266 line and CS line drive strength.
0267 default: 80
0268
0269 rockchip,phy_lpddr4_dq_drv:
0270 deprecated: true
0271 $ref: /schemas/types.yaml#/definitions/uint32
0272 description:
0273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
0274 (including DQS/DQ/DM line) drive strength.
0275 default: 80
0276
0277 rockchip,phy_lpddr4_odt:
0278 deprecated: true
0279 $ref: /schemas/types.yaml#/definitions/uint32
0280 description:
0281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
0282 strength.
0283 default: 60
0284
0285 rockchip,pd-idle-ns:
0286 description:
0287 Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
0288 period in which memories are placed into power-down mode if bus is idle
0289 for PD_IDLE nanoseconds.
0290
0291 rockchip,sr-idle-ns:
0292 description:
0293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
0294 period in which memories are placed into self-refresh mode if bus is idle
0295 for SR_IDLE nanoseconds.
0296 default: 0
0297
0298 rockchip,sr-mc-gate-idle-ns:
0299 description:
0300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
0301 Memories are placed into self-refresh mode and memory controller clock
0302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
0303
0304 rockchip,srpd-lite-idle-ns:
0305 description:
0306 Defines the self-refresh power down idle period in which memories are
0307 placed into self-refresh power down mode if bus is idle for
0308 srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
0309
0310 rockchip,standby-idle-ns:
0311 description:
0312 Defines the standby idle period in which memories are placed into
0313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
0314 if bus is idle for standby_idle nanoseconds.
0315
0316 rockchip,pd-idle-dis-freq-hz:
0317 description:
0318 Defines the power-down idle disable frequency in Hz. When the DDR
0319 frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
0320 See also rockchip,pd-idle-ns.
0321
0322 rockchip,sr-idle-dis-freq-hz:
0323 description:
0324 Defines the self-refresh idle disable frequency in Hz. When the DDR
0325 frequency is greater than sr-idle-dis-freq, self-refresh idle is
0326 disabled. See also rockchip,sr-idle-ns.
0327
0328 rockchip,sr-mc-gate-idle-dis-freq-hz:
0329 description:
0330 Defines the self-refresh and memory-controller clock gating disable
0331 frequency in Hz. When the DDR frequency is greater than
0332 sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
0333 rockchip,sr-mc-gate-idle-ns.
0334
0335 rockchip,srpd-lite-idle-dis-freq-hz:
0336 description:
0337 Defines the self-refresh power down idle disable frequency in Hz. When
0338 the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
0339 not be placed into self-refresh power down mode when idle. See also
0340 rockchip,srpd-lite-idle-ns.
0341
0342 rockchip,standby-idle-dis-freq-hz:
0343 description:
0344 Defines the standby idle disable frequency in Hz. When the DDR frequency
0345 is greater than standby-idle-dis-freq, standby idle is disabled. See also
0346 rockchip,standby-idle-ns.
0347
0348 required:
0349 - compatible
0350 - devfreq-events
0351 - clocks
0352 - clock-names
0353 - operating-points-v2
0354 - center-supply
0355
0356 additionalProperties: false
0357
0358 examples:
0359 - |
0360 #include <dt-bindings/clock/rk3399-cru.h>
0361 #include <dt-bindings/interrupt-controller/arm-gic.h>
0362 memory-controller {
0363 compatible = "rockchip,rk3399-dmc";
0364 devfreq-events = <&dfi>;
0365 rockchip,pmu = <&pmu>;
0366 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0367 clocks = <&cru SCLK_DDRC>;
0368 clock-names = "dmc_clk";
0369 operating-points-v2 = <&dmc_opp_table>;
0370 center-supply = <&ppvar_centerlogic>;
0371 rockchip,pd-idle-ns = <160>;
0372 rockchip,sr-idle-ns = <10240>;
0373 rockchip,sr-mc-gate-idle-ns = <40960>;
0374 rockchip,srpd-lite-idle-ns = <61440>;
0375 rockchip,standby-idle-ns = <81920>;
0376 rockchip,ddr3_odt_dis_freq = <333000000>;
0377 rockchip,lpddr3_odt_dis_freq = <333000000>;
0378 rockchip,lpddr4_odt_dis_freq = <333000000>;
0379 rockchip,pd-idle-dis-freq-hz = <1000000000>;
0380 rockchip,sr-idle-dis-freq-hz = <1000000000>;
0381 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
0382 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
0383 rockchip,standby-idle-dis-freq-hz = <928000000>;
0384 };
