0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Renesas DDR Bus Controllers
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 description: |
0013 Renesas SoCs contain one or more memory controllers. These memory
0014 controllers differ from one SoC variant to another, and are called by
0015 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
0016 (DBSC3)", or "SDRAM Bus State Controller (SBSC)").
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - renesas,dbsc-r8a73a4 # R-Mobile APE6
0022 - renesas,dbsc3-r8a7740 # R-Mobile A1
0023 - renesas,sbsc-sh73a0 # SH-Mobile AG5
0024
0025 reg:
0026 maxItems: 1
0027
0028 interrupts:
0029 maxItems: 2
0030
0031 interrupt-names:
0032 items:
0033 - const: sec # secure interrupt
0034 - const: temp # normal (temperature) interrupt
0035
0036 power-domains:
0037 maxItems: 1
0038
0039 required:
0040 - compatible
0041 - reg
0042 - power-domains
0043
0044 additionalProperties: false
0045
0046 examples:
0047 - |
0048 #include <dt-bindings/interrupt-controller/arm-gic.h>
0049 sbsc1: memory-controller@fe400000 {
0050 compatible = "renesas,sbsc-sh73a0";
0051 reg = <0xfe400000 0x400>;
0052 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0053 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0054 interrupt-names = "sec", "temp";
0055 power-domains = <&pd_a4bc0>;
0056 };
