0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 description: |
0013 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
0014 flush the FIFO between various devices and the DDR. This is mainly used by
0015 the IRQ controller to flush the FIFO before running the interrupt handler of
0016 such devices.
0017
0018 properties:
0019 compatible:
0020 oneOf:
0021 - items:
0022 - const: qca,ar9132-ddr-controller
0023 - const: qca,ar7240-ddr-controller
0024 - items:
0025 - enum:
0026 - qca,ar7100-ddr-controller
0027 - qca,ar7240-ddr-controller
0028
0029 "#qca,ddr-wb-channel-cells":
0030 description: |
0031 Specifies the number of cells needed to encode the write buffer channel
0032 index.
0033 $ref: /schemas/types.yaml#/definitions/uint32
0034 const: 1
0035
0036 reg:
0037 maxItems: 1
0038
0039 required:
0040 - compatible
0041 - "#qca,ddr-wb-channel-cells"
0042 - reg
0043
0044 additionalProperties: false
0045
0046 examples:
0047 - |
0048 ddr_ctrl: memory-controller@18000000 {
0049 compatible = "qca,ar9132-ddr-controller",
0050 "qca,ar7240-ddr-controller";
0051 reg = <0x18000000 0x100>;
0052
0053 #qca,ddr-wb-channel-cells = <1>;
0054 };
0055
0056 interrupt-controller {
0057 // ...
0058 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
0059 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
0060 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
0061 };
