0001 # SPDX-License-Identifier: (GPL-2.0)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra30 SoC Memory Controller
0008
0009 maintainers:
0010 - Dmitry Osipenko <digetx@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Thierry Reding <thierry.reding@gmail.com>
0013
0014 description: |
0015 Tegra30 Memory Controller architecturally consists of the following parts:
0016
0017 Arbitration Domains, which can handle a single request or response per
0018 clock from a group of clients. Typically, a system has a single Arbitration
0019 Domain, but an implementation may divide the client space into multiple
0020 Arbitration Domains to increase the effective system bandwidth.
0021
0022 Protocol Arbiter, which manage a related pool of memory devices. A system
0023 may have a single Protocol Arbiter or multiple Protocol Arbiters.
0024
0025 Memory Crossbar, which routes request and responses between Arbitration
0026 Domains and Protocol Arbiters. In the simplest version of the system, the
0027 Memory Crossbar is just a pass through between a single Arbitration Domain
0028 and a single Protocol Arbiter.
0029
0030 Global Resources, which include things like configuration registers which
0031 are shared across the Memory Subsystem.
0032
0033 The Tegra30 Memory Controller handles memory requests from internal clients
0034 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
0035 SDRAMs.
0036
0037 properties:
0038 compatible:
0039 const: nvidia,tegra30-mc
0040
0041 reg:
0042 maxItems: 1
0043
0044 clocks:
0045 maxItems: 1
0046
0047 clock-names:
0048 items:
0049 - const: mc
0050
0051 interrupts:
0052 maxItems: 1
0053
0054 "#reset-cells":
0055 const: 1
0056
0057 "#iommu-cells":
0058 const: 1
0059
0060 "#interconnect-cells":
0061 const: 1
0062
0063 patternProperties:
0064 "^emc-timings-[0-9]+$":
0065 type: object
0066 properties:
0067 nvidia,ram-code:
0068 $ref: /schemas/types.yaml#/definitions/uint32
0069 description:
0070 Value of RAM_CODE this timing set is used for.
0071
0072 patternProperties:
0073 "^timing-[0-9]+$":
0074 type: object
0075 properties:
0076 clock-frequency:
0077 description:
0078 Memory clock rate in Hz.
0079 minimum: 1000000
0080 maximum: 900000000
0081
0082 nvidia,emem-configuration:
0083 $ref: /schemas/types.yaml#/definitions/uint32-array
0084 description: |
0085 Values to be written to the EMEM register block. See section
0086 "18.13.1 MC Registers" in the TRM.
0087 items:
0088 - description: MC_EMEM_ARB_CFG
0089 - description: MC_EMEM_ARB_OUTSTANDING_REQ
0090 - description: MC_EMEM_ARB_TIMING_RCD
0091 - description: MC_EMEM_ARB_TIMING_RP
0092 - description: MC_EMEM_ARB_TIMING_RC
0093 - description: MC_EMEM_ARB_TIMING_RAS
0094 - description: MC_EMEM_ARB_TIMING_FAW
0095 - description: MC_EMEM_ARB_TIMING_RRD
0096 - description: MC_EMEM_ARB_TIMING_RAP2PRE
0097 - description: MC_EMEM_ARB_TIMING_WAP2PRE
0098 - description: MC_EMEM_ARB_TIMING_R2R
0099 - description: MC_EMEM_ARB_TIMING_W2W
0100 - description: MC_EMEM_ARB_TIMING_R2W
0101 - description: MC_EMEM_ARB_TIMING_W2R
0102 - description: MC_EMEM_ARB_DA_TURNS
0103 - description: MC_EMEM_ARB_DA_COVERS
0104 - description: MC_EMEM_ARB_MISC0
0105 - description: MC_EMEM_ARB_RING1_THROTTLE
0106
0107 required:
0108 - clock-frequency
0109 - nvidia,emem-configuration
0110
0111 additionalProperties: false
0112
0113 required:
0114 - nvidia,ram-code
0115
0116 additionalProperties: false
0117
0118 required:
0119 - compatible
0120 - reg
0121 - interrupts
0122 - clocks
0123 - clock-names
0124 - "#reset-cells"
0125 - "#iommu-cells"
0126 - "#interconnect-cells"
0127
0128 additionalProperties: false
0129
0130 examples:
0131 - |
0132 memory-controller@7000f000 {
0133 compatible = "nvidia,tegra30-mc";
0134 reg = <0x7000f000 0x400>;
0135 clocks = <&tegra_car 32>;
0136 clock-names = "mc";
0137
0138 interrupts = <0 77 4>;
0139
0140 #iommu-cells = <1>;
0141 #reset-cells = <1>;
0142 #interconnect-cells = <1>;
0143
0144 emc-timings-1 {
0145 nvidia,ram-code = <1>;
0146
0147 timing-667000000 {
0148 clock-frequency = <667000000>;
0149
0150 nvidia,emem-configuration = <
0151 0x0000000a /* MC_EMEM_ARB_CFG */
0152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
0153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
0154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
0155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
0156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
0157 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
0158 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0159 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0160 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
0161 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
0162 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0163 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
0164 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
0165 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
0166 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
0167 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
0168 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
0169 >;
0170 };
0171 };
0172 };
