0001 # SPDX-License-Identifier: (GPL-2.0)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra30 SoC External Memory Controller
0008
0009 maintainers:
0010 - Dmitry Osipenko <digetx@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Thierry Reding <thierry.reding@gmail.com>
0013
0014 description: |
0015 The EMC interfaces with the off-chip SDRAM to service the request stream
0016 sent from Memory Controller. The EMC also has various performance-affecting
0017 settings beyond the obvious SDRAM configuration parameters and initialization
0018 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
0019 LPDDR3, and DDR3.
0020
0021 properties:
0022 compatible:
0023 const: nvidia,tegra30-emc
0024
0025 reg:
0026 maxItems: 1
0027
0028 clocks:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 "#interconnect-cells":
0035 const: 0
0036
0037 nvidia,memory-controller:
0038 $ref: /schemas/types.yaml#/definitions/phandle
0039 description:
0040 Phandle of the Memory Controller node.
0041
0042 power-domains:
0043 maxItems: 1
0044 description:
0045 Phandle of the SoC "core" power domain.
0046
0047 operating-points-v2:
0048 description:
0049 Should contain freqs and voltages and opp-supported-hw property, which
0050 is a bitfield indicating SoC speedo ID mask.
0051
0052 patternProperties:
0053 "^emc-timings-[0-9]+$":
0054 type: object
0055 properties:
0056 nvidia,ram-code:
0057 $ref: /schemas/types.yaml#/definitions/uint32
0058 description:
0059 Value of RAM_CODE this timing set is used for.
0060
0061 patternProperties:
0062 "^timing-[0-9]+$":
0063 type: object
0064 properties:
0065 clock-frequency:
0066 description:
0067 Memory clock rate in Hz.
0068 minimum: 1000000
0069 maximum: 900000000
0070
0071 nvidia,emc-auto-cal-interval:
0072 description:
0073 Pad calibration interval in microseconds.
0074 $ref: /schemas/types.yaml#/definitions/uint32
0075 minimum: 0
0076 maximum: 2097151
0077
0078 nvidia,emc-mode-1:
0079 $ref: /schemas/types.yaml#/definitions/uint32
0080 description:
0081 Mode Register 1.
0082
0083 nvidia,emc-mode-2:
0084 $ref: /schemas/types.yaml#/definitions/uint32
0085 description:
0086 Mode Register 2.
0087
0088 nvidia,emc-mode-reset:
0089 $ref: /schemas/types.yaml#/definitions/uint32
0090 description:
0091 Mode Register 0.
0092
0093 nvidia,emc-zcal-cnt-long:
0094 description:
0095 Number of EMC clocks to wait before issuing any commands after
0096 sending ZCAL_MRW_CMD.
0097 $ref: /schemas/types.yaml#/definitions/uint32
0098 minimum: 0
0099 maximum: 1023
0100
0101 nvidia,emc-cfg-dyn-self-ref:
0102 type: boolean
0103 description:
0104 Dynamic self-refresh enabled.
0105
0106 nvidia,emc-cfg-periodic-qrst:
0107 type: boolean
0108 description:
0109 FBIO "read" FIFO periodic resetting enabled.
0110
0111 nvidia,emc-configuration:
0112 description:
0113 EMC timing characterization data. These are the registers
0114 (see section "18.13.2 EMC Registers" in the TRM) whose values
0115 need to be specified, according to the board documentation.
0116 $ref: /schemas/types.yaml#/definitions/uint32-array
0117 items:
0118 - description: EMC_RC
0119 - description: EMC_RFC
0120 - description: EMC_RAS
0121 - description: EMC_RP
0122 - description: EMC_R2W
0123 - description: EMC_W2R
0124 - description: EMC_R2P
0125 - description: EMC_W2P
0126 - description: EMC_RD_RCD
0127 - description: EMC_WR_RCD
0128 - description: EMC_RRD
0129 - description: EMC_REXT
0130 - description: EMC_WEXT
0131 - description: EMC_WDV
0132 - description: EMC_QUSE
0133 - description: EMC_QRST
0134 - description: EMC_QSAFE
0135 - description: EMC_RDV
0136 - description: EMC_REFRESH
0137 - description: EMC_BURST_REFRESH_NUM
0138 - description: EMC_PRE_REFRESH_REQ_CNT
0139 - description: EMC_PDEX2WR
0140 - description: EMC_PDEX2RD
0141 - description: EMC_PCHG2PDEN
0142 - description: EMC_ACT2PDEN
0143 - description: EMC_AR2PDEN
0144 - description: EMC_RW2PDEN
0145 - description: EMC_TXSR
0146 - description: EMC_TXSRDLL
0147 - description: EMC_TCKE
0148 - description: EMC_TFAW
0149 - description: EMC_TRPAB
0150 - description: EMC_TCLKSTABLE
0151 - description: EMC_TCLKSTOP
0152 - description: EMC_TREFBW
0153 - description: EMC_QUSE_EXTRA
0154 - description: EMC_FBIO_CFG6
0155 - description: EMC_ODT_WRITE
0156 - description: EMC_ODT_READ
0157 - description: EMC_FBIO_CFG5
0158 - description: EMC_CFG_DIG_DLL
0159 - description: EMC_CFG_DIG_DLL_PERIOD
0160 - description: EMC_DLL_XFORM_DQS0
0161 - description: EMC_DLL_XFORM_DQS1
0162 - description: EMC_DLL_XFORM_DQS2
0163 - description: EMC_DLL_XFORM_DQS3
0164 - description: EMC_DLL_XFORM_DQS4
0165 - description: EMC_DLL_XFORM_DQS5
0166 - description: EMC_DLL_XFORM_DQS6
0167 - description: EMC_DLL_XFORM_DQS7
0168 - description: EMC_DLL_XFORM_QUSE0
0169 - description: EMC_DLL_XFORM_QUSE1
0170 - description: EMC_DLL_XFORM_QUSE2
0171 - description: EMC_DLL_XFORM_QUSE3
0172 - description: EMC_DLL_XFORM_QUSE4
0173 - description: EMC_DLL_XFORM_QUSE5
0174 - description: EMC_DLL_XFORM_QUSE6
0175 - description: EMC_DLL_XFORM_QUSE7
0176 - description: EMC_DLI_TRIM_TXDQS0
0177 - description: EMC_DLI_TRIM_TXDQS1
0178 - description: EMC_DLI_TRIM_TXDQS2
0179 - description: EMC_DLI_TRIM_TXDQS3
0180 - description: EMC_DLI_TRIM_TXDQS4
0181 - description: EMC_DLI_TRIM_TXDQS5
0182 - description: EMC_DLI_TRIM_TXDQS6
0183 - description: EMC_DLI_TRIM_TXDQS7
0184 - description: EMC_DLL_XFORM_DQ0
0185 - description: EMC_DLL_XFORM_DQ1
0186 - description: EMC_DLL_XFORM_DQ2
0187 - description: EMC_DLL_XFORM_DQ3
0188 - description: EMC_XM2CMDPADCTRL
0189 - description: EMC_XM2DQSPADCTRL2
0190 - description: EMC_XM2DQPADCTRL2
0191 - description: EMC_XM2CLKPADCTRL
0192 - description: EMC_XM2COMPPADCTRL
0193 - description: EMC_XM2VTTGENPADCTRL
0194 - description: EMC_XM2VTTGENPADCTRL2
0195 - description: EMC_XM2QUSEPADCTRL
0196 - description: EMC_XM2DQSPADCTRL3
0197 - description: EMC_CTT_TERM_CTRL
0198 - description: EMC_ZCAL_INTERVAL
0199 - description: EMC_ZCAL_WAIT_CNT
0200 - description: EMC_MRS_WAIT_CNT
0201 - description: EMC_AUTO_CAL_CONFIG
0202 - description: EMC_CTT
0203 - description: EMC_CTT_DURATION
0204 - description: EMC_DYN_SELF_REF_CONTROL
0205 - description: EMC_FBIO_SPARE
0206 - description: EMC_CFG_RSV
0207
0208 required:
0209 - clock-frequency
0210 - nvidia,emc-auto-cal-interval
0211 - nvidia,emc-mode-1
0212 - nvidia,emc-mode-2
0213 - nvidia,emc-mode-reset
0214 - nvidia,emc-zcal-cnt-long
0215 - nvidia,emc-configuration
0216
0217 additionalProperties: false
0218
0219 required:
0220 - nvidia,ram-code
0221
0222 additionalProperties: false
0223
0224 required:
0225 - compatible
0226 - reg
0227 - interrupts
0228 - clocks
0229 - nvidia,memory-controller
0230 - "#interconnect-cells"
0231 - operating-points-v2
0232
0233 additionalProperties: false
0234
0235 examples:
0236 - |
0237 external-memory-controller@7000f400 {
0238 compatible = "nvidia,tegra30-emc";
0239 reg = <0x7000f400 0x400>;
0240 interrupts = <0 78 4>;
0241 clocks = <&tegra_car 57>;
0242
0243 nvidia,memory-controller = <&mc>;
0244 operating-points-v2 = <&dvfs_opp_table>;
0245 power-domains = <&domain>;
0246
0247 #interconnect-cells = <0>;
0248
0249 emc-timings-1 {
0250 nvidia,ram-code = <1>;
0251
0252 timing-667000000 {
0253 clock-frequency = <667000000>;
0254
0255 nvidia,emc-auto-cal-interval = <0x001fffff>;
0256 nvidia,emc-mode-1 = <0x80100002>;
0257 nvidia,emc-mode-2 = <0x80200018>;
0258 nvidia,emc-mode-reset = <0x80000b71>;
0259 nvidia,emc-zcal-cnt-long = <0x00000040>;
0260 nvidia,emc-cfg-periodic-qrst;
0261
0262 nvidia,emc-configuration = <
0263 0x00000020 /* EMC_RC */
0264 0x0000006a /* EMC_RFC */
0265 0x00000017 /* EMC_RAS */
0266 0x00000007 /* EMC_RP */
0267 0x00000005 /* EMC_R2W */
0268 0x0000000c /* EMC_W2R */
0269 0x00000003 /* EMC_R2P */
0270 0x00000011 /* EMC_W2P */
0271 0x00000007 /* EMC_RD_RCD */
0272 0x00000007 /* EMC_WR_RCD */
0273 0x00000002 /* EMC_RRD */
0274 0x00000001 /* EMC_REXT */
0275 0x00000000 /* EMC_WEXT */
0276 0x00000007 /* EMC_WDV */
0277 0x0000000a /* EMC_QUSE */
0278 0x00000009 /* EMC_QRST */
0279 0x0000000b /* EMC_QSAFE */
0280 0x00000011 /* EMC_RDV */
0281 0x00001412 /* EMC_REFRESH */
0282 0x00000000 /* EMC_BURST_REFRESH_NUM */
0283 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0284 0x00000002 /* EMC_PDEX2WR */
0285 0x0000000e /* EMC_PDEX2RD */
0286 0x00000001 /* EMC_PCHG2PDEN */
0287 0x00000000 /* EMC_ACT2PDEN */
0288 0x0000000c /* EMC_AR2PDEN */
0289 0x00000016 /* EMC_RW2PDEN */
0290 0x00000072 /* EMC_TXSR */
0291 0x00000200 /* EMC_TXSRDLL */
0292 0x00000005 /* EMC_TCKE */
0293 0x00000015 /* EMC_TFAW */
0294 0x00000000 /* EMC_TRPAB */
0295 0x00000006 /* EMC_TCLKSTABLE */
0296 0x00000007 /* EMC_TCLKSTOP */
0297 0x00001453 /* EMC_TREFBW */
0298 0x0000000b /* EMC_QUSE_EXTRA */
0299 0x00000006 /* EMC_FBIO_CFG6 */
0300 0x00000000 /* EMC_ODT_WRITE */
0301 0x00000000 /* EMC_ODT_READ */
0302 0x00005088 /* EMC_FBIO_CFG5 */
0303 0xf00b0191 /* EMC_CFG_DIG_DLL */
0304 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0305 0x00000008 /* EMC_DLL_XFORM_DQS0 */
0306 0x00000008 /* EMC_DLL_XFORM_DQS1 */
0307 0x00000008 /* EMC_DLL_XFORM_DQS2 */
0308 0x00000008 /* EMC_DLL_XFORM_DQS3 */
0309 0x0000000a /* EMC_DLL_XFORM_DQS4 */
0310 0x0000000a /* EMC_DLL_XFORM_DQS5 */
0311 0x0000000a /* EMC_DLL_XFORM_DQS6 */
0312 0x0000000a /* EMC_DLL_XFORM_DQS7 */
0313 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
0314 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
0315 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
0316 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
0317 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0318 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0319 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0320 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0321 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0322 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0323 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0324 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0325 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0326 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0327 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0328 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0329 0x0000000a /* EMC_DLL_XFORM_DQ0 */
0330 0x0000000a /* EMC_DLL_XFORM_DQ1 */
0331 0x0000000a /* EMC_DLL_XFORM_DQ2 */
0332 0x0000000a /* EMC_DLL_XFORM_DQ3 */
0333 0x000002a0 /* EMC_XM2CMDPADCTRL */
0334 0x0800013d /* EMC_XM2DQSPADCTRL2 */
0335 0x22220000 /* EMC_XM2DQPADCTRL2 */
0336 0x77fff884 /* EMC_XM2CLKPADCTRL */
0337 0x01f1f501 /* EMC_XM2COMPPADCTRL */
0338 0x07077404 /* EMC_XM2VTTGENPADCTRL */
0339 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0340 0x080001e8 /* EMC_XM2QUSEPADCTRL */
0341 0x0c000021 /* EMC_XM2DQSPADCTRL3 */
0342 0x00000802 /* EMC_CTT_TERM_CTRL */
0343 0x00020000 /* EMC_ZCAL_INTERVAL */
0344 0x00000100 /* EMC_ZCAL_WAIT_CNT */
0345 0x0155000c /* EMC_MRS_WAIT_CNT */
0346 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0347 0x00000000 /* EMC_CTT */
0348 0x00000000 /* EMC_CTT_DURATION */
0349 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0350 0xe8000000 /* EMC_FBIO_SPARE */
0351 0xff00ff49 /* EMC_CFG_RSV */
0352 >;
0353 };
0354 };
0355 };
