0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra20 SoC External Memory Controller
0008
0009 maintainers:
0010 - Dmitry Osipenko <digetx@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Thierry Reding <thierry.reding@gmail.com>
0013
0014 description: |
0015 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
0016 service the request stream sent from Memory Controller. The EMC also has
0017 various performance-affecting settings beyond the obvious SDRAM configuration
0018 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
0019 standard protocols: DDR1, LPDDR2 and DDR2.
0020
0021 properties:
0022 compatible:
0023 const: nvidia,tegra20-emc
0024
0025 reg:
0026 maxItems: 1
0027
0028 clocks:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 "#address-cells":
0035 const: 1
0036
0037 "#size-cells":
0038 const: 0
0039
0040 "#interconnect-cells":
0041 const: 0
0042
0043 nvidia,memory-controller:
0044 $ref: /schemas/types.yaml#/definitions/phandle
0045 description:
0046 Phandle of the Memory Controller node.
0047
0048 power-domains:
0049 maxItems: 1
0050 description:
0051 Phandle of the SoC "core" power domain.
0052
0053 operating-points-v2:
0054 description:
0055 Should contain freqs and voltages and opp-supported-hw property, which
0056 is a bitfield indicating SoC process ID mask.
0057
0058 nvidia,use-ram-code:
0059 type: boolean
0060 description:
0061 If present, the emc-tables@ sub-nodes will be addressed.
0062
0063 $defs:
0064 emc-table:
0065 type: object
0066 properties:
0067 compatible:
0068 const: nvidia,tegra20-emc-table
0069
0070 clock-frequency:
0071 description:
0072 Memory clock rate in kHz.
0073 minimum: 1000
0074 maximum: 900000
0075
0076 reg:
0077 maxItems: 1
0078 description:
0079 Either an opaque enumerator to tell different tables apart, or
0080 the valid frequency for which the table should be used (in kHz).
0081
0082 nvidia,emc-registers:
0083 description:
0084 EMC timing characterization data. These are the registers
0085 (see section "15.4.1 EMC Registers" in the TRM) whose values
0086 need to be specified, according to the board documentation.
0087 $ref: /schemas/types.yaml#/definitions/uint32-array
0088 items:
0089 - description: EMC_RC
0090 - description: EMC_RFC
0091 - description: EMC_RAS
0092 - description: EMC_RP
0093 - description: EMC_R2W
0094 - description: EMC_W2R
0095 - description: EMC_R2P
0096 - description: EMC_W2P
0097 - description: EMC_RD_RCD
0098 - description: EMC_WR_RCD
0099 - description: EMC_RRD
0100 - description: EMC_REXT
0101 - description: EMC_WDV
0102 - description: EMC_QUSE
0103 - description: EMC_QRST
0104 - description: EMC_QSAFE
0105 - description: EMC_RDV
0106 - description: EMC_REFRESH
0107 - description: EMC_BURST_REFRESH_NUM
0108 - description: EMC_PDEX2WR
0109 - description: EMC_PDEX2RD
0110 - description: EMC_PCHG2PDEN
0111 - description: EMC_ACT2PDEN
0112 - description: EMC_AR2PDEN
0113 - description: EMC_RW2PDEN
0114 - description: EMC_TXSR
0115 - description: EMC_TCKE
0116 - description: EMC_TFAW
0117 - description: EMC_TRPAB
0118 - description: EMC_TCLKSTABLE
0119 - description: EMC_TCLKSTOP
0120 - description: EMC_TREFBW
0121 - description: EMC_QUSE_EXTRA
0122 - description: EMC_FBIO_CFG6
0123 - description: EMC_ODT_WRITE
0124 - description: EMC_ODT_READ
0125 - description: EMC_FBIO_CFG5
0126 - description: EMC_CFG_DIG_DLL
0127 - description: EMC_DLL_XFORM_DQS
0128 - description: EMC_DLL_XFORM_QUSE
0129 - description: EMC_ZCAL_REF_CNT
0130 - description: EMC_ZCAL_WAIT_CNT
0131 - description: EMC_AUTO_CAL_INTERVAL
0132 - description: EMC_CFG_CLKTRIM_0
0133 - description: EMC_CFG_CLKTRIM_1
0134 - description: EMC_CFG_CLKTRIM_2
0135
0136 required:
0137 - clock-frequency
0138 - compatible
0139 - reg
0140 - nvidia,emc-registers
0141
0142 additionalProperties: false
0143
0144 patternProperties:
0145 "^emc-table@[0-9]+$":
0146 $ref: "#/$defs/emc-table"
0147
0148 "^emc-tables@[a-z0-9-]+$":
0149 type: object
0150 properties:
0151 reg:
0152 maxItems: 1
0153 description:
0154 An opaque enumerator to tell different tables apart.
0155
0156 nvidia,ram-code:
0157 $ref: /schemas/types.yaml#/definitions/uint32
0158 description:
0159 Value of RAM_CODE this timing set is used for.
0160
0161 "#address-cells":
0162 const: 1
0163
0164 "#size-cells":
0165 const: 0
0166
0167 lpddr2:
0168 $ref: "ddr/jedec,lpddr2.yaml#"
0169 type: object
0170
0171 patternProperties:
0172 "^emc-table@[0-9]+$":
0173 $ref: "#/$defs/emc-table"
0174
0175 oneOf:
0176 - required:
0177 - nvidia,ram-code
0178
0179 - required:
0180 - lpddr2
0181
0182 additionalProperties: false
0183
0184 required:
0185 - compatible
0186 - reg
0187 - interrupts
0188 - clocks
0189 - nvidia,memory-controller
0190 - "#interconnect-cells"
0191 - operating-points-v2
0192
0193 additionalProperties: false
0194
0195 examples:
0196 - |
0197 external-memory-controller@7000f400 {
0198 compatible = "nvidia,tegra20-emc";
0199 reg = <0x7000f400 0x400>;
0200 interrupts = <0 78 4>;
0201 clocks = <&clock_controller 57>;
0202
0203 nvidia,memory-controller = <&mc>;
0204 operating-points-v2 = <&dvfs_opp_table>;
0205 power-domains = <&domain>;
0206
0207 #interconnect-cells = <0>;
0208 #address-cells = <1>;
0209 #size-cells = <0>;
0210
0211 nvidia,use-ram-code;
0212
0213 emc-tables@0 {
0214 nvidia,ram-code = <0>;
0215 reg = <0>;
0216
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219
0220 emc-table@333000 {
0221 reg = <333000>;
0222 compatible = "nvidia,tegra20-emc-table";
0223 clock-frequency = <333000>;
0224 nvidia,emc-registers = <0x00000018 0x00000033
0225 0x00000012 0x00000004 0x00000004 0x00000005
0226 0x00000003 0x0000000c 0x00000006 0x00000006
0227 0x00000003 0x00000001 0x00000004 0x00000005
0228 0x00000004 0x00000009 0x0000000d 0x00000bff
0229 0x00000000 0x00000003 0x00000003 0x00000006
0230 0x00000006 0x00000001 0x00000011 0x000000c8
0231 0x00000003 0x0000000e 0x00000007 0x00000008
0232 0x00000002 0x00000000 0x00000000 0x00000002
0233 0x00000000 0x00000000 0x00000083 0xf0440303
0234 0x007fe010 0x00001414 0x00000000 0x00000000
0235 0x00000000 0x00000000 0x00000000 0x00000000>;
0236 };
0237 };
0238
0239 emc-tables@1 {
0240 reg = <1>;
0241
0242 lpddr2 {
0243 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
0244 revision-id1 = <1>;
0245 density = <2048>;
0246 io-width = <16>;
0247 };
0248 };
0249 };
