0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra186 (and later) SoC Memory Controller
0008
0009 maintainers:
0010 - Jon Hunter <jonathanh@nvidia.com>
0011 - Thierry Reding <thierry.reding@gmail.com>
0012
0013 description: |
0014 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
0015 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
0016 handles memory requests for 40-bit virtual addresses from internal clients
0017 and arbitrates among them to allocate memory bandwidth.
0018
0019 Up to 15 GiB of physical memory can be supported. Security features such as
0020 encryption of traffic to and from DRAM via general security apertures are
0021 available for video and other secure applications, as well as DRAM ECC for
0022 automotive safety applications (single bit error correction and double bit
0023 error detection).
0024
0025 properties:
0026 $nodename:
0027 pattern: "^memory-controller@[0-9a-f]+$"
0028
0029 compatible:
0030 items:
0031 - enum:
0032 - nvidia,tegra186-mc
0033 - nvidia,tegra194-mc
0034 - nvidia,tegra234-mc
0035
0036 reg:
0037 minItems: 6
0038 maxItems: 18
0039
0040 reg-names:
0041 minItems: 6
0042 maxItems: 18
0043
0044 interrupts:
0045 items:
0046 - description: MC general interrupt
0047
0048 "#address-cells":
0049 const: 2
0050
0051 "#size-cells":
0052 const: 2
0053
0054 ranges: true
0055
0056 dma-ranges: true
0057
0058 "#interconnect-cells":
0059 const: 1
0060
0061 patternProperties:
0062 "^external-memory-controller@[0-9a-f]+$":
0063 description:
0064 The bulk of the work involved in controlling the external memory
0065 controller on NVIDIA Tegra186 and later is performed on the BPMP. This
0066 coprocessor exposes the EMC clock that is used to set the frequency at
0067 which the external memory is clocked and a remote procedure call that
0068 can be used to obtain the set of available frequencies.
0069 type: object
0070 properties:
0071 compatible:
0072 items:
0073 - enum:
0074 - nvidia,tegra186-emc
0075 - nvidia,tegra194-emc
0076 - nvidia,tegra234-emc
0077
0078 reg:
0079 minItems: 1
0080 maxItems: 2
0081
0082 interrupts:
0083 items:
0084 - description: EMC general interrupt
0085
0086 clocks:
0087 items:
0088 - description: external memory clock
0089
0090 clock-names:
0091 items:
0092 - const: emc
0093
0094 "#interconnect-cells":
0095 const: 0
0096
0097 nvidia,bpmp:
0098 $ref: /schemas/types.yaml#/definitions/phandle
0099 description:
0100 phandle of the node representing the BPMP
0101
0102 allOf:
0103 - if:
0104 properties:
0105 compatible:
0106 const: nvidia,tegra186-emc
0107 then:
0108 properties:
0109 reg:
0110 maxItems: 1
0111
0112 - if:
0113 properties:
0114 compatible:
0115 const: nvidia,tegra194-emc
0116 then:
0117 properties:
0118 reg:
0119 minItems: 2
0120
0121 - if:
0122 properties:
0123 compatible:
0124 const: nvidia,tegra234-emc
0125 then:
0126 properties:
0127 reg:
0128 minItems: 2
0129
0130 additionalProperties: false
0131
0132 required:
0133 - compatible
0134 - reg
0135 - interrupts
0136 - clocks
0137 - clock-names
0138 - "#interconnect-cells"
0139 - nvidia,bpmp
0140
0141 allOf:
0142 - if:
0143 properties:
0144 compatible:
0145 const: nvidia,tegra186-mc
0146 then:
0147 properties:
0148 reg:
0149 maxItems: 6
0150 description: 5 memory controller channels and 1 for stream-id registers
0151
0152 reg-names:
0153 items:
0154 - const: sid
0155 - const: broadcast
0156 - const: ch0
0157 - const: ch1
0158 - const: ch2
0159 - const: ch3
0160
0161 - if:
0162 properties:
0163 compatible:
0164 const: nvidia,tegra194-mc
0165 then:
0166 properties:
0167 reg:
0168 minItems: 18
0169 description: 17 memory controller channels and 1 for stream-id registers
0170
0171 reg-names:
0172 items:
0173 - const: sid
0174 - const: broadcast
0175 - const: ch0
0176 - const: ch1
0177 - const: ch2
0178 - const: ch3
0179 - const: ch4
0180 - const: ch5
0181 - const: ch6
0182 - const: ch7
0183 - const: ch8
0184 - const: ch9
0185 - const: ch10
0186 - const: ch11
0187 - const: ch12
0188 - const: ch13
0189 - const: ch14
0190 - const: ch15
0191
0192 - if:
0193 properties:
0194 compatible:
0195 const: nvidia,tegra234-mc
0196 then:
0197 properties:
0198 reg:
0199 minItems: 18
0200 description: 17 memory controller channels and 1 for stream-id registers
0201
0202 reg-names:
0203 items:
0204 - const: sid
0205 - const: broadcast
0206 - const: ch0
0207 - const: ch1
0208 - const: ch2
0209 - const: ch3
0210 - const: ch4
0211 - const: ch5
0212 - const: ch6
0213 - const: ch7
0214 - const: ch8
0215 - const: ch9
0216 - const: ch10
0217 - const: ch11
0218 - const: ch12
0219 - const: ch13
0220 - const: ch14
0221 - const: ch15
0222
0223 additionalProperties: false
0224
0225 required:
0226 - compatible
0227 - reg
0228 - reg-names
0229 - interrupts
0230 - "#address-cells"
0231 - "#size-cells"
0232
0233 examples:
0234 - |
0235 #include <dt-bindings/clock/tegra186-clock.h>
0236 #include <dt-bindings/interrupt-controller/arm-gic.h>
0237
0238 bus {
0239 #address-cells = <2>;
0240 #size-cells = <2>;
0241
0242 memory-controller@2c00000 {
0243 compatible = "nvidia,tegra186-mc";
0244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
0245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
0246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
0247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
0248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
0249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
0250 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
0251 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0252
0253 #address-cells = <2>;
0254 #size-cells = <2>;
0255
0256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
0257
0258 /*
0259 * Memory clients have access to all 40 bits that the memory
0260 * controller can address.
0261 */
0262 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
0263
0264 external-memory-controller@2c60000 {
0265 compatible = "nvidia,tegra186-emc";
0266 reg = <0x0 0x02c60000 0x0 0x50000>;
0267 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
0268 clocks = <&bpmp TEGRA186_CLK_EMC>;
0269 clock-names = "emc";
0270
0271 #interconnect-cells = <0>;
0272
0273 nvidia,bpmp = <&bpmp>;
0274 };
0275 };
0276 };
