bindings/memory-controllers/nvidia%2Ctegra124-mc.yaml

0001 # SPDX-License-Identifier: (GPL-2.0)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra124 SoC Memory Controller
0008
0009 maintainers:
0010   - Jon Hunter <jonathanh@nvidia.com>
0011   - Thierry Reding <thierry.reding@gmail.com>
0012
0013 description: |
0014   Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
0015   These are interleaved to provide high performance with the load shared across
0016   two memory channels. The Tegra124 Memory Controller handles memory requests
0017   from internal clients and arbitrates among them to allocate memory bandwidth
0018   for DDR3L and LPDDR3 SDRAMs.
0019
0020 properties:
0021   compatible:
0022     const: nvidia,tegra124-mc
0023
0024   reg:
0025     maxItems: 1
0026
0027   clocks:
0028     maxItems: 1
0029
0030   clock-names:
0031     items:
0032       - const: mc
0033
0034   interrupts:
0035     maxItems: 1
0036
0037   "#reset-cells":
0038     const: 1
0039
0040   "#iommu-cells":
0041     const: 1
0042
0043   "#interconnect-cells":
0044     const: 1
0045
0046 patternProperties:
0047   "^emc-timings-[0-9]+$":
0048     type: object
0049     properties:
0050       nvidia,ram-code:
0051         $ref: /schemas/types.yaml#/definitions/uint32
0052         description:
0053           Value of RAM_CODE this timing set is used for.
0054
0055     patternProperties:
0056       "^timing-[0-9]+$":
0057         type: object
0058         properties:
0059           clock-frequency:
0060             description:
0061               Memory clock rate in Hz.
0062             minimum: 1000000
0063             maximum: 1066000000
0064
0065           nvidia,emem-configuration:
0066             $ref: /schemas/types.yaml#/definitions/uint32-array
0067             description: |
0068               Values to be written to the EMEM register block. See section
0069               "15.6.1 MC Registers" in the TRM.
0070             items:
0071               - description: MC_EMEM_ARB_CFG
0072               - description: MC_EMEM_ARB_OUTSTANDING_REQ
0073               - description: MC_EMEM_ARB_TIMING_RCD
0074               - description: MC_EMEM_ARB_TIMING_RP
0075               - description: MC_EMEM_ARB_TIMING_RC
0076               - description: MC_EMEM_ARB_TIMING_RAS
0077               - description: MC_EMEM_ARB_TIMING_FAW
0078               - description: MC_EMEM_ARB_TIMING_RRD
0079               - description: MC_EMEM_ARB_TIMING_RAP2PRE
0080               - description: MC_EMEM_ARB_TIMING_WAP2PRE
0081               - description: MC_EMEM_ARB_TIMING_R2R
0082               - description: MC_EMEM_ARB_TIMING_W2W
0083               - description: MC_EMEM_ARB_TIMING_R2W
0084               - description: MC_EMEM_ARB_TIMING_W2R
0085               - description: MC_EMEM_ARB_DA_TURNS
0086               - description: MC_EMEM_ARB_DA_COVERS
0087               - description: MC_EMEM_ARB_MISC0
0088               - description: MC_EMEM_ARB_MISC1
0089               - description: MC_EMEM_ARB_RING1_THROTTLE
0090
0091         required:
0092           - clock-frequency
0093           - nvidia,emem-configuration
0094
0095         additionalProperties: false
0096
0097     required:
0098       - nvidia,ram-code
0099
0100     additionalProperties: false
0101
0102 required:
0103   - compatible
0104   - reg
0105   - interrupts
0106   - clocks
0107   - clock-names
0108   - "#reset-cells"
0109   - "#iommu-cells"
0110   - "#interconnect-cells"
0111
0112 additionalProperties: false
0113
0114 examples:
0115   - |
0116     memory-controller@70019000 {
0117         compatible = "nvidia,tegra124-mc";
0118         reg = <0x70019000 0x1000>;
0119         clocks = <&tegra_car 32>;
0120         clock-names = "mc";
0121
0122         interrupts = <0 77 4>;
0123
0124         #iommu-cells = <1>;
0125         #reset-cells = <1>;
0126         #interconnect-cells = <1>;
0127
0128         emc-timings-3 {
0129             nvidia,ram-code = <3>;
0130
0131             timing-12750000 {
0132                 clock-frequency = <12750000>;
0133
0134                 nvidia,emem-configuration = <
0135                     0x40040001 /* MC_EMEM_ARB_CFG */
0136                     0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0137                     0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0138                     0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0139                     0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0140                     0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0141                     0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0142                     0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0143                     0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0144                     0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0145                     0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0146                     0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0147                     0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0148                     0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0149                     0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0150                     0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0151                     0x77e30303 /* MC_EMEM_ARB_MISC0 */
0152                     0x70000f03 /* MC_EMEM_ARB_MISC1 */
0153                     0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
0154                 >;
0155             };
0156         };
0157     };