0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra124 SoC External Memory Controller
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 The EMC interfaces with the off-chip SDRAM to service the request stream
0015 sent from the memory controller.
0016
0017 properties:
0018 compatible:
0019 const: nvidia,tegra124-emc
0020
0021 reg:
0022 maxItems: 1
0023
0024 clocks:
0025 items:
0026 - description: external memory clock
0027
0028 clock-names:
0029 items:
0030 - const: emc
0031
0032 "#interconnect-cells":
0033 const: 0
0034
0035 nvidia,memory-controller:
0036 $ref: /schemas/types.yaml#/definitions/phandle
0037 description:
0038 phandle of the memory controller node
0039
0040 power-domains:
0041 maxItems: 1
0042 description:
0043 Phandle of the SoC "core" power domain.
0044
0045 operating-points-v2:
0046 description:
0047 Should contain freqs and voltages and opp-supported-hw property, which
0048 is a bitfield indicating SoC speedo ID mask.
0049
0050 patternProperties:
0051 "^emc-timings-[0-9]+$":
0052 type: object
0053 properties:
0054 nvidia,ram-code:
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 description:
0057 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
0058 this timing set is used for
0059
0060 patternProperties:
0061 "^timing-[0-9]+$":
0062 type: object
0063 properties:
0064 clock-frequency:
0065 description:
0066 external memory clock rate in Hz
0067 minimum: 1000000
0068 maximum: 1000000000
0069
0070 nvidia,emc-auto-cal-config:
0071 $ref: /schemas/types.yaml#/definitions/uint32
0072 description:
0073 value of the EMC_AUTO_CAL_CONFIG register for this set of
0074 timings
0075
0076 nvidia,emc-auto-cal-config2:
0077 $ref: /schemas/types.yaml#/definitions/uint32
0078 description:
0079 value of the EMC_AUTO_CAL_CONFIG2 register for this set of
0080 timings
0081
0082 nvidia,emc-auto-cal-config3:
0083 $ref: /schemas/types.yaml#/definitions/uint32
0084 description:
0085 value of the EMC_AUTO_CAL_CONFIG3 register for this set of
0086 timings
0087
0088 nvidia,emc-auto-cal-interval:
0089 description:
0090 pad calibration interval in microseconds
0091 $ref: /schemas/types.yaml#/definitions/uint32
0092 minimum: 0
0093 maximum: 2097151
0094
0095 nvidia,emc-bgbias-ctl0:
0096 $ref: /schemas/types.yaml#/definitions/uint32
0097 description:
0098 value of the EMC_BGBIAS_CTL0 register for this set of timings
0099
0100 nvidia,emc-cfg:
0101 $ref: /schemas/types.yaml#/definitions/uint32
0102 description:
0103 value of the EMC_CFG register for this set of timings
0104
0105 nvidia,emc-cfg-2:
0106 $ref: /schemas/types.yaml#/definitions/uint32
0107 description:
0108 value of the EMC_CFG_2 register for this set of timings
0109
0110 nvidia,emc-ctt-term-ctrl:
0111 $ref: /schemas/types.yaml#/definitions/uint32
0112 description:
0113 value of the EMC_CTT_TERM_CTRL register for this set of timings
0114
0115 nvidia,emc-mode-1:
0116 $ref: /schemas/types.yaml#/definitions/uint32
0117 description:
0118 value of the EMC_MRW register for this set of timings
0119
0120 nvidia,emc-mode-2:
0121 $ref: /schemas/types.yaml#/definitions/uint32
0122 description:
0123 value of the EMC_MRW2 register for this set of timings
0124
0125 nvidia,emc-mode-4:
0126 $ref: /schemas/types.yaml#/definitions/uint32
0127 description:
0128 value of the EMC_MRW4 register for this set of timings
0129
0130 nvidia,emc-mode-reset:
0131 $ref: /schemas/types.yaml#/definitions/uint32
0132 description:
0133 reset value of the EMC_MRS register for this set of timings
0134
0135 nvidia,emc-mrs-wait-cnt:
0136 $ref: /schemas/types.yaml#/definitions/uint32
0137 description:
0138 value of the EMR_MRS_WAIT_CNT register for this set of timings
0139
0140 nvidia,emc-sel-dpd-ctrl:
0141 $ref: /schemas/types.yaml#/definitions/uint32
0142 description:
0143 value of the EMC_SEL_DPD_CTRL register for this set of timings
0144
0145 nvidia,emc-xm2dqspadctrl2:
0146 $ref: /schemas/types.yaml#/definitions/uint32
0147 description:
0148 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
0149
0150 nvidia,emc-zcal-cnt-long:
0151 description:
0152 number of EMC clocks to wait before issuing any commands after
0153 clock change
0154 $ref: /schemas/types.yaml#/definitions/uint32
0155 minimum: 0
0156 maximum: 1023
0157
0158 nvidia,emc-zcal-interval:
0159 $ref: /schemas/types.yaml#/definitions/uint32
0160 description:
0161 value of the EMC_ZCAL_INTERVAL register for this set of timings
0162
0163 nvidia,emc-configuration:
0164 description:
0165 EMC timing characterization data. These are the registers (see
0166 section "15.6.2 EMC Registers" in the TRM) whose values need to
0167 be specified, according to the board documentation.
0168 $ref: /schemas/types.yaml#/definitions/uint32-array
0169 items:
0170 - description: EMC_RC
0171 - description: EMC_RFC
0172 - description: EMC_RFC_SLR
0173 - description: EMC_RAS
0174 - description: EMC_RP
0175 - description: EMC_R2W
0176 - description: EMC_W2R
0177 - description: EMC_R2P
0178 - description: EMC_W2P
0179 - description: EMC_RD_RCD
0180 - description: EMC_WR_RCD
0181 - description: EMC_RRD
0182 - description: EMC_REXT
0183 - description: EMC_WEXT
0184 - description: EMC_WDV
0185 - description: EMC_WDV_MASK
0186 - description: EMC_QUSE
0187 - description: EMC_QUSE_WIDTH
0188 - description: EMC_IBDLY
0189 - description: EMC_EINPUT
0190 - description: EMC_EINPUT_DURATION
0191 - description: EMC_PUTERM_EXTRA
0192 - description: EMC_PUTERM_WIDTH
0193 - description: EMC_PUTERM_ADJ
0194 - description: EMC_CDB_CNTL_1
0195 - description: EMC_CDB_CNTL_2
0196 - description: EMC_CDB_CNTL_3
0197 - description: EMC_QRST
0198 - description: EMC_QSAFE
0199 - description: EMC_RDV
0200 - description: EMC_RDV_MASK
0201 - description: EMC_REFRESH
0202 - description: EMC_BURST_REFRESH_NUM
0203 - description: EMC_PRE_REFRESH_REQ_CNT
0204 - description: EMC_PDEX2WR
0205 - description: EMC_PDEX2RD
0206 - description: EMC_PCHG2PDEN
0207 - description: EMC_ACT2PDEN
0208 - description: EMC_AR2PDEN
0209 - description: EMC_RW2PDEN
0210 - description: EMC_TXSR
0211 - description: EMC_TXSRDLL
0212 - description: EMC_TCKE
0213 - description: EMC_TCKESR
0214 - description: EMC_TPD
0215 - description: EMC_TFAW
0216 - description: EMC_TRPAB
0217 - description: EMC_TCLKSTABLE
0218 - description: EMC_TCLKSTOP
0219 - description: EMC_TREFBW
0220 - description: EMC_FBIO_CFG6
0221 - description: EMC_ODT_WRITE
0222 - description: EMC_ODT_READ
0223 - description: EMC_FBIO_CFG5
0224 - description: EMC_CFG_DIG_DLL
0225 - description: EMC_CFG_DIG_DLL_PERIOD
0226 - description: EMC_DLL_XFORM_DQS0
0227 - description: EMC_DLL_XFORM_DQS1
0228 - description: EMC_DLL_XFORM_DQS2
0229 - description: EMC_DLL_XFORM_DQS3
0230 - description: EMC_DLL_XFORM_DQS4
0231 - description: EMC_DLL_XFORM_DQS5
0232 - description: EMC_DLL_XFORM_DQS6
0233 - description: EMC_DLL_XFORM_DQS7
0234 - description: EMC_DLL_XFORM_DQS8
0235 - description: EMC_DLL_XFORM_DQS9
0236 - description: EMC_DLL_XFORM_DQS10
0237 - description: EMC_DLL_XFORM_DQS11
0238 - description: EMC_DLL_XFORM_DQS12
0239 - description: EMC_DLL_XFORM_DQS13
0240 - description: EMC_DLL_XFORM_DQS14
0241 - description: EMC_DLL_XFORM_DQS15
0242 - description: EMC_DLL_XFORM_QUSE0
0243 - description: EMC_DLL_XFORM_QUSE1
0244 - description: EMC_DLL_XFORM_QUSE2
0245 - description: EMC_DLL_XFORM_QUSE3
0246 - description: EMC_DLL_XFORM_QUSE4
0247 - description: EMC_DLL_XFORM_QUSE5
0248 - description: EMC_DLL_XFORM_QUSE6
0249 - description: EMC_DLL_XFORM_QUSE7
0250 - description: EMC_DLL_XFORM_ADDR0
0251 - description: EMC_DLL_XFORM_ADDR1
0252 - description: EMC_DLL_XFORM_ADDR2
0253 - description: EMC_DLL_XFORM_ADDR3
0254 - description: EMC_DLL_XFORM_ADDR4
0255 - description: EMC_DLL_XFORM_ADDR5
0256 - description: EMC_DLL_XFORM_QUSE8
0257 - description: EMC_DLL_XFORM_QUSE9
0258 - description: EMC_DLL_XFORM_QUSE10
0259 - description: EMC_DLL_XFORM_QUSE11
0260 - description: EMC_DLL_XFORM_QUSE12
0261 - description: EMC_DLL_XFORM_QUSE13
0262 - description: EMC_DLL_XFORM_QUSE14
0263 - description: EMC_DLL_XFORM_QUSE15
0264 - description: EMC_DLI_TRIM_TXDQS0
0265 - description: EMC_DLI_TRIM_TXDQS1
0266 - description: EMC_DLI_TRIM_TXDQS2
0267 - description: EMC_DLI_TRIM_TXDQS3
0268 - description: EMC_DLI_TRIM_TXDQS4
0269 - description: EMC_DLI_TRIM_TXDQS5
0270 - description: EMC_DLI_TRIM_TXDQS6
0271 - description: EMC_DLI_TRIM_TXDQS7
0272 - description: EMC_DLI_TRIM_TXDQS8
0273 - description: EMC_DLI_TRIM_TXDQS9
0274 - description: EMC_DLI_TRIM_TXDQS10
0275 - description: EMC_DLI_TRIM_TXDQS11
0276 - description: EMC_DLI_TRIM_TXDQS12
0277 - description: EMC_DLI_TRIM_TXDQS13
0278 - description: EMC_DLI_TRIM_TXDQS14
0279 - description: EMC_DLI_TRIM_TXDQS15
0280 - description: EMC_DLL_XFORM_DQ0
0281 - description: EMC_DLL_XFORM_DQ1
0282 - description: EMC_DLL_XFORM_DQ2
0283 - description: EMC_DLL_XFORM_DQ3
0284 - description: EMC_DLL_XFORM_DQ4
0285 - description: EMC_DLL_XFORM_DQ5
0286 - description: EMC_DLL_XFORM_DQ6
0287 - description: EMC_DLL_XFORM_DQ7
0288 - description: EMC_XM2CMDPADCTRL
0289 - description: EMC_XM2CMDPADCTRL4
0290 - description: EMC_XM2CMDPADCTRL5
0291 - description: EMC_XM2DQPADCTRL2
0292 - description: EMC_XM2DQPADCTRL3
0293 - description: EMC_XM2CLKPADCTRL
0294 - description: EMC_XM2CLKPADCTRL2
0295 - description: EMC_XM2COMPPADCTRL
0296 - description: EMC_XM2VTTGENPADCTRL
0297 - description: EMC_XM2VTTGENPADCTRL2
0298 - description: EMC_XM2VTTGENPADCTRL3
0299 - description: EMC_XM2DQSPADCTRL3
0300 - description: EMC_XM2DQSPADCTRL4
0301 - description: EMC_XM2DQSPADCTRL5
0302 - description: EMC_XM2DQSPADCTRL6
0303 - description: EMC_DSR_VTTGEN_DRV
0304 - description: EMC_TXDSRVTTGEN
0305 - description: EMC_FBIO_SPARE
0306 - description: EMC_ZCAL_WAIT_CNT
0307 - description: EMC_MRS_WAIT_CNT2
0308 - description: EMC_CTT
0309 - description: EMC_CTT_DURATION
0310 - description: EMC_CFG_PIPE
0311 - description: EMC_DYN_SELF_REF_CONTROL
0312 - description: EMC_QPOP
0313
0314 required:
0315 - clock-frequency
0316 - nvidia,emc-auto-cal-config
0317 - nvidia,emc-auto-cal-config2
0318 - nvidia,emc-auto-cal-config3
0319 - nvidia,emc-auto-cal-interval
0320 - nvidia,emc-bgbias-ctl0
0321 - nvidia,emc-cfg
0322 - nvidia,emc-cfg-2
0323 - nvidia,emc-ctt-term-ctrl
0324 - nvidia,emc-mode-1
0325 - nvidia,emc-mode-2
0326 - nvidia,emc-mode-4
0327 - nvidia,emc-mode-reset
0328 - nvidia,emc-mrs-wait-cnt
0329 - nvidia,emc-sel-dpd-ctrl
0330 - nvidia,emc-xm2dqspadctrl2
0331 - nvidia,emc-zcal-cnt-long
0332 - nvidia,emc-zcal-interval
0333 - nvidia,emc-configuration
0334
0335 additionalProperties: false
0336
0337 required:
0338 - compatible
0339 - reg
0340 - clocks
0341 - clock-names
0342 - nvidia,memory-controller
0343 - "#interconnect-cells"
0344 - operating-points-v2
0345
0346 additionalProperties: false
0347
0348 examples:
0349 - |
0350 #include <dt-bindings/clock/tegra124-car.h>
0351 #include <dt-bindings/interrupt-controller/arm-gic.h>
0352
0353 mc: memory-controller@70019000 {
0354 compatible = "nvidia,tegra124-mc";
0355 reg = <0x70019000 0x1000>;
0356 clocks = <&tegra_car TEGRA124_CLK_MC>;
0357 clock-names = "mc";
0358
0359 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0360
0361 #iommu-cells = <1>;
0362 #reset-cells = <1>;
0363 #interconnect-cells = <1>;
0364 };
0365
0366 external-memory-controller@7001b000 {
0367 compatible = "nvidia,tegra124-emc";
0368 reg = <0x7001b000 0x1000>;
0369 clocks = <&car TEGRA124_CLK_EMC>;
0370 clock-names = "emc";
0371
0372 nvidia,memory-controller = <&mc>;
0373 operating-points-v2 = <&dvfs_opp_table>;
0374 power-domains = <&domain>;
0375
0376 #interconnect-cells = <0>;
0377
0378 emc-timings-0 {
0379 nvidia,ram-code = <3>;
0380
0381 timing-0 {
0382 clock-frequency = <12750000>;
0383
0384 nvidia,emc-auto-cal-config = <0xa1430000>;
0385 nvidia,emc-auto-cal-config2 = <0x00000000>;
0386 nvidia,emc-auto-cal-config3 = <0x00000000>;
0387 nvidia,emc-auto-cal-interval = <0x001fffff>;
0388 nvidia,emc-bgbias-ctl0 = <0x00000008>;
0389 nvidia,emc-cfg = <0x73240000>;
0390 nvidia,emc-cfg-2 = <0x000008c5>;
0391 nvidia,emc-ctt-term-ctrl = <0x00000802>;
0392 nvidia,emc-mode-1 = <0x80100003>;
0393 nvidia,emc-mode-2 = <0x80200008>;
0394 nvidia,emc-mode-4 = <0x00000000>;
0395 nvidia,emc-mode-reset = <0x80001221>;
0396 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
0397 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
0398 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
0399 nvidia,emc-zcal-cnt-long = <0x00000042>;
0400 nvidia,emc-zcal-interval = <0x00000000>;
0401
0402 nvidia,emc-configuration = <
0403 0x00000000 /* EMC_RC */
0404 0x00000003 /* EMC_RFC */
0405 0x00000000 /* EMC_RFC_SLR */
0406 0x00000000 /* EMC_RAS */
0407 0x00000000 /* EMC_RP */
0408 0x00000004 /* EMC_R2W */
0409 0x0000000a /* EMC_W2R */
0410 0x00000003 /* EMC_R2P */
0411 0x0000000b /* EMC_W2P */
0412 0x00000000 /* EMC_RD_RCD */
0413 0x00000000 /* EMC_WR_RCD */
0414 0x00000003 /* EMC_RRD */
0415 0x00000003 /* EMC_REXT */
0416 0x00000000 /* EMC_WEXT */
0417 0x00000006 /* EMC_WDV */
0418 0x00000006 /* EMC_WDV_MASK */
0419 0x00000006 /* EMC_QUSE */
0420 0x00000002 /* EMC_QUSE_WIDTH */
0421 0x00000000 /* EMC_IBDLY */
0422 0x00000005 /* EMC_EINPUT */
0423 0x00000005 /* EMC_EINPUT_DURATION */
0424 0x00010000 /* EMC_PUTERM_EXTRA */
0425 0x00000003 /* EMC_PUTERM_WIDTH */
0426 0x00000000 /* EMC_PUTERM_ADJ */
0427 0x00000000 /* EMC_CDB_CNTL_1 */
0428 0x00000000 /* EMC_CDB_CNTL_2 */
0429 0x00000000 /* EMC_CDB_CNTL_3 */
0430 0x00000004 /* EMC_QRST */
0431 0x0000000c /* EMC_QSAFE */
0432 0x0000000d /* EMC_RDV */
0433 0x0000000f /* EMC_RDV_MASK */
0434 0x00000060 /* EMC_REFRESH */
0435 0x00000000 /* EMC_BURST_REFRESH_NUM */
0436 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
0437 0x00000002 /* EMC_PDEX2WR */
0438 0x00000002 /* EMC_PDEX2RD */
0439 0x00000001 /* EMC_PCHG2PDEN */
0440 0x00000000 /* EMC_ACT2PDEN */
0441 0x00000007 /* EMC_AR2PDEN */
0442 0x0000000f /* EMC_RW2PDEN */
0443 0x00000005 /* EMC_TXSR */
0444 0x00000005 /* EMC_TXSRDLL */
0445 0x00000004 /* EMC_TCKE */
0446 0x00000005 /* EMC_TCKESR */
0447 0x00000004 /* EMC_TPD */
0448 0x00000000 /* EMC_TFAW */
0449 0x00000000 /* EMC_TRPAB */
0450 0x00000005 /* EMC_TCLKSTABLE */
0451 0x00000005 /* EMC_TCLKSTOP */
0452 0x00000064 /* EMC_TREFBW */
0453 0x00000000 /* EMC_FBIO_CFG6 */
0454 0x00000000 /* EMC_ODT_WRITE */
0455 0x00000000 /* EMC_ODT_READ */
0456 0x106aa298 /* EMC_FBIO_CFG5 */
0457 0x002c00a0 /* EMC_CFG_DIG_DLL */
0458 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0459 0x00064000 /* EMC_DLL_XFORM_DQS0 */
0460 0x00064000 /* EMC_DLL_XFORM_DQS1 */
0461 0x00064000 /* EMC_DLL_XFORM_DQS2 */
0462 0x00064000 /* EMC_DLL_XFORM_DQS3 */
0463 0x00064000 /* EMC_DLL_XFORM_DQS4 */
0464 0x00064000 /* EMC_DLL_XFORM_DQS5 */
0465 0x00064000 /* EMC_DLL_XFORM_DQS6 */
0466 0x00064000 /* EMC_DLL_XFORM_DQS7 */
0467 0x00064000 /* EMC_DLL_XFORM_DQS8 */
0468 0x00064000 /* EMC_DLL_XFORM_DQS9 */
0469 0x00064000 /* EMC_DLL_XFORM_DQS10 */
0470 0x00064000 /* EMC_DLL_XFORM_DQS11 */
0471 0x00064000 /* EMC_DLL_XFORM_DQS12 */
0472 0x00064000 /* EMC_DLL_XFORM_DQS13 */
0473 0x00064000 /* EMC_DLL_XFORM_DQS14 */
0474 0x00064000 /* EMC_DLL_XFORM_DQS15 */
0475 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0476 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0477 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0478 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0479 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0480 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0481 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0482 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0483 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
0484 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
0485 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
0486 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
0487 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
0488 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
0489 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
0490 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
0491 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
0492 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
0493 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
0494 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
0495 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
0496 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
0497 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0498 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0499 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0500 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0501 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0502 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0503 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0504 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0505 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
0506 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
0507 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
0508 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
0509 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
0510 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
0511 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
0512 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
0513 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
0514 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
0515 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
0516 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
0517 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
0518 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
0519 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
0520 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
0521 0x10000280 /* EMC_XM2CMDPADCTRL */
0522 0x00000000 /* EMC_XM2CMDPADCTRL4 */
0523 0x00111111 /* EMC_XM2CMDPADCTRL5 */
0524 0x00000000 /* EMC_XM2DQPADCTRL2 */
0525 0x00000000 /* EMC_XM2DQPADCTRL3 */
0526 0x77ffc081 /* EMC_XM2CLKPADCTRL */
0527 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
0528 0x81f1f108 /* EMC_XM2COMPPADCTRL */
0529 0x07070004 /* EMC_XM2VTTGENPADCTRL */
0530 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
0531 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
0532 0x51451400 /* EMC_XM2DQSPADCTRL3 */
0533 0x00514514 /* EMC_XM2DQSPADCTRL4 */
0534 0x00514514 /* EMC_XM2DQSPADCTRL5 */
0535 0x51451400 /* EMC_XM2DQSPADCTRL6 */
0536 0x0000003f /* EMC_DSR_VTTGEN_DRV */
0537 0x00000007 /* EMC_TXDSRVTTGEN */
0538 0x00000000 /* EMC_FBIO_SPARE */
0539 0x00000042 /* EMC_ZCAL_WAIT_CNT */
0540 0x000e000e /* EMC_MRS_WAIT_CNT2 */
0541 0x00000000 /* EMC_CTT */
0542 0x00000003 /* EMC_CTT_DURATION */
0543 0x0000f2f3 /* EMC_CFG_PIPE */
0544 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
0545 0x0000000a /* EMC_QPOP */
0546 >;
0547 };
0548 };
0549 };
