0001 Device tree bindings for MVEBU Device Bus controllers
0002
0003 The Device Bus controller available in some Marvell's SoC allows to control
0004 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
0005 The actual devices are instantiated from the child nodes of a Device Bus node.
0006
0007 Required properties:
0008
0009 - compatible: Armada 370/XP SoC are supported using the
0010 "marvell,mvebu-devbus" compatible string.
0011
0012 Orion5x SoC are supported using the
0013 "marvell,orion-devbus" compatible string.
0014
0015 - reg: A resource specifier for the register space.
0016 This is the base address of a chip select within
0017 the controller's register space.
0018 (see the example below)
0019
0020 - #address-cells: Must be set to 1
0021 - #size-cells: Must be set to 1
0022 - ranges: Must be set up to reflect the memory layout with four
0023 integer values for each chip-select line in use:
0024 0 <physical address of mapping> <size>
0025
0026 Optional properties:
0027
0028 - devbus,keep-config This property can optionally be used to keep
0029 using the timing parameters set by the
0030 bootloader. It makes all the timing properties
0031 described below unused.
0032
0033 Timing properties for child nodes:
0034
0035 Read parameters:
0036
0037 - devbus,turn-off-ps: Defines the time during which the controller does not
0038 drive the AD bus after the completion of a device read.
0039 This prevents contentions on the Device Bus after a read
0040 cycle from a slow device.
0041 Mandatory, except if devbus,keep-config is used.
0042
0043 - devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
0044 Mandatory, except if devbus,keep-config is used.
0045
0046 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
0047 to read data sample. This parameter is useful for
0048 synchronous pipelined devices, where the address
0049 precedes the read data by one or two cycles.
0050 Mandatory, except if devbus,keep-config is used.
0051
0052 - devbus,acc-first-ps: Defines the time delay from the negation of
0053 ALE[0] to the cycle that the first read data is sampled
0054 by the controller.
0055 Mandatory, except if devbus,keep-config is used.
0056
0057 - devbus,acc-next-ps: Defines the time delay between the cycle that
0058 samples data N and the cycle that samples data N+1
0059 (in burst accesses).
0060 Mandatory, except if devbus,keep-config is used.
0061
0062 - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
0063 DEV_OEn assertion. If set to 0 (default),
0064 DEV_OEn and DEV_CSn are asserted at the same cycle.
0065 This parameter has no affect on <acc-first-ps> parameter
0066 (no affect on first data sample). Set <rd-setup-ps>
0067 to a value smaller than <acc-first-ps>.
0068 Mandatory for "marvell,mvebu-devbus" compatible string,
0069 except if devbus,keep-config is used.
0070
0071 - devbus,rd-hold-ps: Defines the time between the last data sample to the
0072 de-assertion of DEV_CSn. If set to 0 (default),
0073 DEV_OEn and DEV_CSn are de-asserted at the same cycle
0074 (the cycle of the last data sample).
0075 This parameter has no affect on DEV_OEn de-assertion.
0076 DEV_OEn is always de-asserted the next cycle after
0077 last data sampled. Also this parameter has no
0078 affect on <turn-off-ps> parameter.
0079 Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
0080 Mandatory for "marvell,mvebu-devbus" compatible string,
0081 except if devbus,keep-config is used.
0082
0083 Write parameters:
0084
0085 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
0086 to the DEV_WEn assertion.
0087 Mandatory.
0088
0089 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
0090 A[2:0] and Data are kept valid as long as DEV_WEn
0091 is active. This parameter defines the setup time of
0092 address and data to DEV_WEn rise.
0093 Mandatory.
0094
0095 - devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
0096 inactive (high) between data beats of a burst write.
0097 DEV_A[2:0] and Data are kept valid (do not toggle) for
0098 <wr-high-ps> - <tick> ps.
0099 This parameter defines the hold time of address and
0100 data after DEV_WEn rise.
0101 Mandatory.
0102
0103 - devbus,sync-enable: Synchronous device enable.
0104 1: True
0105 0: False
0106 Mandatory for "marvell,mvebu-devbus" compatible string,
0107 except if devbus,keep-config is used.
0108
0109 An example for an Armada XP GP board, with a 16 MiB NOR device as child
0110 is showed below. Note that the Device Bus driver is in charge of allocating
0111 the mbus address decoding window for each of its child devices.
0112 The window is created using the chip select specified in the child
0113 device node together with the base address and size specified in the ranges
0114 property. For instance, in the example below the allocated decoding window
0115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
0116 for chip select 0 (a.k.a DEV_BOOTCS).
0117
0118 This address window handling is done in this mvebu-devbus only as a temporary
0119 solution. It will be removed when the support for mbus device tree binding is
0120 added.
0121
0122 The reg property implicitly specifies the chip select as this:
0123
0124 0x10400: DEV_BOOTCS
0125 0x10408: DEV_CS0
0126 0x10410: DEV_CS1
0127 0x10418: DEV_CS2
0128 0x10420: DEV_CS3
0129
0130 Example:
0131
0132 devbus-bootcs@d0010400 {
0133 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
0134 #address-cells = <1>;
0135 #size-cells = <1>;
0136
0137 /* Device Bus parameters are required */
0138
0139 /* Read parameters */
0140 devbus,bus-width = <8>;
0141 devbus,turn-off-ps = <60000>;
0142 devbus,badr-skew-ps = <0>;
0143 devbus,acc-first-ps = <124000>;
0144 devbus,acc-next-ps = <248000>;
0145 devbus,rd-setup-ps = <0>;
0146 devbus,rd-hold-ps = <0>;
0147
0148 /* Write parameters */
0149 devbus,sync-enable = <0>;
0150 devbus,wr-high-ps = <60000>;
0151 devbus,wr-low-ps = <60000>;
0152 devbus,ale-wr-ps = <60000>;
0153
0154 flash@0 {
0155 compatible = "cfi-flash";
0156
0157 /* 16 MiB */
0158 reg = <0 0x1000000>;
0159 bank-width = <2>;
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162
0163 /*
0164 * We split the 16 MiB in two partitions,
0165 * just as an example.
0166 */
0167 partition@0 {
0168 label = "First";
0169 reg = <0 0x800000>;
0170 };
0171
0172 partition@800000 {
0173 label = "Second";
0174 reg = <0x800000 0x800000>;
0175 };
0176 };
0177 };
