0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: i.MX8M DDR Controller
0008
0009 maintainers:
0010 - Peng Fan <peng.fan@nxp.com>
0011
0012 description:
0013 The DDRC block is integrated in i.MX8M for interfacing with DDR based
0014 memories.
0015
0016 It supports switching between different frequencies at runtime but during
0017 this process RAM itself becomes briefly inaccessible so actual frequency
0018 switching is implemented by TF-A code which runs from a SRAM area.
0019
0020 The Linux driver for the DDRC doesn't even map registers (they're included
0021 for the sake of "describing hardware"), it mostly just exposes firmware
0022 capabilities through standard Linux mechanism like devfreq and OPP tables.
0023
0024 properties:
0025 compatible:
0026 items:
0027 - enum:
0028 - fsl,imx8mn-ddrc
0029 - fsl,imx8mm-ddrc
0030 - fsl,imx8mq-ddrc
0031 - const: fsl,imx8m-ddrc
0032
0033 reg:
0034 maxItems: 1
0035 description:
0036 Base address and size of DDRC CTL area.
0037 This is not currently mapped by the imx8m-ddrc driver.
0038
0039 clocks:
0040 maxItems: 4
0041
0042 clock-names:
0043 items:
0044 - const: core
0045 - const: pll
0046 - const: alt
0047 - const: apb
0048
0049 operating-points-v2: true
0050 opp-table: true
0051
0052 required:
0053 - reg
0054 - compatible
0055 - clocks
0056 - clock-names
0057
0058 additionalProperties: false
0059
0060 examples:
0061 - |
0062 #include <dt-bindings/clock/imx8mm-clock.h>
0063 ddrc: memory-controller@3d400000 {
0064 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
0065 reg = <0x3d400000 0x400000>;
0066 clock-names = "core", "pll", "alt", "apb";
0067 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
0068 <&clk IMX8MM_DRAM_PLL>,
0069 <&clk IMX8MM_CLK_DRAM_ALT>,
0070 <&clk IMX8MM_CLK_DRAM_APB>;
0071 operating-points-v2 = <&ddrc_opp_table>;
0072 };
