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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: FSL/NXP Integrated Flash Controller
0008 
0009 maintainers:
0010   - Li Yang <leoyang.li@nxp.com>
0011 
0012 description: |
0013   NXP's integrated flash controller (IFC) is an advanced version of the
0014   enhanced local bus controller which includes similar programming and signal
0015   interfaces with an extended feature set. The IFC provides access to multiple
0016   external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
0017   SRAM and other memories where address and data are shared on a bus.
0018 
0019 properties:
0020   $nodename:
0021     pattern: "^memory-controller@[0-9a-f]+$"
0022 
0023   compatible:
0024     const: fsl,ifc
0025 
0026   "#address-cells":
0027     enum: [2, 3]
0028     description: |
0029       Should be either two or three.  The first cell is the chipselect
0030       number, and the remaining cells are the offset into the chipselect.
0031 
0032   "#size-cells":
0033     enum: [1, 2]
0034     description: |
0035       Either one or two, depending on how large each chipselect can be.
0036 
0037   reg:
0038     maxItems: 1
0039 
0040   interrupts:
0041     minItems: 1
0042     maxItems: 2
0043     description: |
0044       IFC may have one or two interrupts.  If two interrupt specifiers are
0045       present, the first is the "common" interrupt (CM_EVTER_STAT), and the
0046       second is the NAND interrupt (NAND_EVTER_STAT).  If there is only one,
0047       that interrupt reports both types of event.
0048 
0049   little-endian:
0050     type: boolean
0051     description: |
0052       If this property is absent, the big-endian mode will be in use as default
0053       for registers.
0054 
0055   ranges:
0056     description: |
0057       Each range corresponds to a single chipselect, and covers the entire
0058       access window as configured.
0059 
0060 patternProperties:
0061   "^.*@[a-f0-9]+(,[a-f0-9]+)+$":
0062     type: object
0063     description: |
0064       Child device nodes describe the devices connected to IFC such as NOR (e.g.
0065       cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
0066       like FPGAs, CPLDs, etc.
0067 
0068     required:
0069       - compatible
0070       - reg
0071 
0072 required:
0073   - compatible
0074   - reg
0075   - interrupts
0076 
0077 additionalProperties: false
0078 
0079 examples:
0080   - |
0081     soc {
0082         #address-cells = <2>;
0083         #size-cells = <2>;
0084 
0085         memory-controller@ffe1e000 {
0086             compatible = "fsl,ifc";
0087             #address-cells = <2>;
0088             #size-cells = <1>;
0089             reg = <0x0 0xffe1e000 0 0x2000>;
0090             interrupts = <16 2 19 2>;
0091             little-endian;
0092 
0093             /* NOR, NAND Flashes and CPLD on board */
0094             ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
0095                      <0x1 0x0 0x0 0xffa00000 0x00010000>,
0096                      <0x3 0x0 0x0 0xffb00000 0x00020000>;
0097 
0098             flash@0,0 {
0099                 #address-cells = <1>;
0100                 #size-cells = <1>;
0101                 compatible = "cfi-flash";
0102                 reg = <0x0 0x0 0x2000000>;
0103                 bank-width = <2>;
0104                 device-width = <1>;
0105 
0106                 partition@0 {
0107                     /* 32MB for user data */
0108                     reg = <0x0 0x02000000>;
0109                     label = "NOR Data";
0110                 };
0111             };
0112         };
0113     };