0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos SoC SROM Controller driver
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 description: |+
0013 The SROM controller can be used to attach external peripherals. In this case
0014 extra properties, describing the bus behind it, should be specified.
0015
0016 properties:
0017 compatible:
0018 items:
0019 - const: samsung,exynos4210-srom
0020
0021 reg:
0022 maxItems: 1
0023
0024 "#address-cells":
0025 const: 2
0026
0027 "#size-cells":
0028 const: 1
0029
0030 ranges:
0031 minItems: 1
0032 maxItems: 4
0033 description: |
0034 Reflects the memory layout with four integer values per bank. Format:
0035 <bank-number> 0 <parent address of bank> <size>
0036 Up to four banks are supported.
0037
0038 patternProperties:
0039 "^.*@[0-3],[a-f0-9]+$":
0040 type: object
0041 description:
0042 The actual device nodes should be added as subnodes to the SROMc node.
0043 These subnodes, in addition to regular device specification, should
0044 contain the following properties, describing configuration
0045 of the relevant SROM bank.
0046
0047 properties:
0048 reg:
0049 description:
0050 Bank number, base address (relative to start of the bank) and size
0051 of the memory mapped for the device. Note that base address will be
0052 typically 0 as this is the start of the bank.
0053 maxItems: 1
0054
0055 reg-io-width:
0056 enum: [1, 2]
0057 description:
0058 Data width in bytes (1 or 2). If omitted, default of 1 is used.
0059
0060 samsung,srom-page-mode:
0061 description:
0062 If page mode is set, 4 data page mode will be configured,
0063 else normal (1 data) page mode will be set.
0064 type: boolean
0065
0066 samsung,srom-timing:
0067 $ref: /schemas/types.yaml#/definitions/uint32-array
0068 items:
0069 minItems: 6
0070 maxItems: 6
0071 description: |
0072 Array of 6 integers, specifying bank timings in the following order:
0073 Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
0074 Each value is specified in cycles and has the following meaning
0075 and valid range:
0076 Tacp: Page mode access cycle at Page mode (0 - 15)
0077 Tcah: Address holding time after CSn (0 - 15)
0078 Tcoh: Chip selection hold on OEn (0 - 15)
0079 Tacc: Access cycle (0 - 31, the actual time is N + 1)
0080 Tcos: Chip selection set-up before OEn (0 - 15)
0081 Tacs: Address set-up before CSn (0 - 15)
0082
0083 required:
0084 - reg
0085 - samsung,srom-timing
0086
0087 required:
0088 - compatible
0089 - reg
0090
0091 additionalProperties: false
0092
0093 examples:
0094 - |
0095 // Example: basic definition, no banks are configured
0096 memory-controller@12560000 {
0097 compatible = "samsung,exynos4210-srom";
0098 reg = <0x12560000 0x14>;
0099 };
0100
0101 - |
0102 // Example: SROMc with SMSC911x ethernet chip on bank 3
0103 memory-controller@12570000 {
0104 #address-cells = <2>;
0105 #size-cells = <1>;
0106 ranges = <0 0 0x04000000 0x20000 // Bank0
0107 1 0 0x05000000 0x20000 // Bank1
0108 2 0 0x06000000 0x20000 // Bank2
0109 3 0 0x07000000 0x20000>; // Bank3
0110
0111 compatible = "samsung,exynos4210-srom";
0112 reg = <0x12570000 0x14>;
0113
0114 ethernet@3,0 {
0115 compatible = "smsc,lan9115";
0116 reg = <3 0 0x10000>; // Bank 3, offset = 0
0117 phy-mode = "mii";
0118 interrupt-parent = <&gpx0>;
0119 interrupts = <5 8>;
0120 reg-io-width = <2>;
0121 smsc,irq-push-pull;
0122 smsc,force-internal-phy;
0123
0124 samsung,srom-page-mode;
0125 samsung,srom-timing = <9 12 1 9 1 1>;
0126 };
0127 };
