0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 properties:
0013 compatible:
0014 items:
0015 - enum:
0016 - samsung,K3QF2F20DB
0017 - const: jedec,lpddr3
0018
0019 '#address-cells':
0020 const: 1
0021 deprecated: true
0022
0023 density:
0024 $ref: /schemas/types.yaml#/definitions/uint32
0025 description: |
0026 Density in megabits of SDRAM chip.
0027 enum:
0028 - 4096
0029 - 8192
0030 - 16384
0031 - 32768
0032
0033 io-width:
0034 $ref: /schemas/types.yaml#/definitions/uint32
0035 description: |
0036 IO bus width in bits of SDRAM chip.
0037 enum:
0038 - 32
0039 - 16
0040
0041 manufacturer-id:
0042 $ref: /schemas/types.yaml#/definitions/uint32
0043 description: |
0044 Manufacturer ID value read from Mode Register 5. The property is
0045 deprecated, manufacturer should be derived from the compatible.
0046 deprecated: true
0047
0048 revision-id:
0049 $ref: /schemas/types.yaml#/definitions/uint32-array
0050 minItems: 2
0051 maxItems: 2
0052 items:
0053 maximum: 255
0054 description: |
0055 Revision value of SDRAM chip read from Mode Registers 6 and 7.
0056
0057 '#size-cells':
0058 const: 0
0059 deprecated: true
0060
0061 tCKE-min-tck:
0062 $ref: /schemas/types.yaml#/definitions/uint32
0063 maximum: 15
0064 description: |
0065 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
0066 of clock cycles.
0067
0068 tCKESR-min-tck:
0069 $ref: /schemas/types.yaml#/definitions/uint32
0070 maximum: 15
0071 description: |
0072 CKE minimum pulse width during SELF REFRESH (low pulse width during
0073 SELF REFRESH) in terms of number of clock cycles.
0074
0075 tDQSCK-min-tck:
0076 $ref: /schemas/types.yaml#/definitions/uint32
0077 maximum: 15
0078 description: |
0079 DQS output data access time from CK_t/CK_c in terms of number of clock
0080 cycles.
0081
0082 tFAW-min-tck:
0083 $ref: /schemas/types.yaml#/definitions/uint32
0084 maximum: 63
0085 description: |
0086 Four-bank activate window in terms of number of clock cycles.
0087
0088 tMRD-min-tck:
0089 $ref: /schemas/types.yaml#/definitions/uint32
0090 maximum: 15
0091 description: |
0092 Mode register set command delay in terms of number of clock cycles.
0093
0094 tR2R-C2C-min-tck:
0095 $ref: /schemas/types.yaml#/definitions/uint32
0096 enum: [0, 1]
0097 description: |
0098 Additional READ-to-READ delay in chip-to-chip cases in terms of number
0099 of clock cycles.
0100
0101 tRAS-min-tck:
0102 $ref: /schemas/types.yaml#/definitions/uint32
0103 maximum: 63
0104 description: |
0105 Row active time in terms of number of clock cycles.
0106
0107 tRC-min-tck:
0108 $ref: /schemas/types.yaml#/definitions/uint32
0109 maximum: 63
0110 description: |
0111 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
0112
0113 tRCD-min-tck:
0114 $ref: /schemas/types.yaml#/definitions/uint32
0115 maximum: 15
0116 description: |
0117 RAS-to-CAS delay in terms of number of clock cycles.
0118
0119 tRFC-min-tck:
0120 $ref: /schemas/types.yaml#/definitions/uint32
0121 maximum: 255
0122 description: |
0123 Refresh Cycle time in terms of number of clock cycles.
0124
0125 tRL-min-tck:
0126 $ref: /schemas/types.yaml#/definitions/uint32
0127 maximum: 15
0128 description: |
0129 READ data latency in terms of number of clock cycles.
0130
0131 tRPab-min-tck:
0132 $ref: /schemas/types.yaml#/definitions/uint32
0133 maximum: 15
0134 description: |
0135 Row precharge time (all banks) in terms of number of clock cycles.
0136
0137 tRPpb-min-tck:
0138 $ref: /schemas/types.yaml#/definitions/uint32
0139 maximum: 15
0140 description: |
0141 Row precharge time (single banks) in terms of number of clock cycles.
0142
0143 tRRD-min-tck:
0144 $ref: /schemas/types.yaml#/definitions/uint32
0145 maximum: 15
0146 description: |
0147 Active bank A to active bank B in terms of number of clock cycles.
0148
0149 tRTP-min-tck:
0150 $ref: /schemas/types.yaml#/definitions/uint32
0151 maximum: 15
0152 description: |
0153 Internal READ to PRECHARGE command delay in terms of number of clock
0154 cycles.
0155
0156 tW2W-C2C-min-tck:
0157 $ref: /schemas/types.yaml#/definitions/uint32
0158 enum: [0, 1]
0159 description: |
0160 Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
0161 of clock cycles.
0162
0163 tWL-min-tck:
0164 $ref: /schemas/types.yaml#/definitions/uint32
0165 maximum: 15
0166 description: |
0167 WRITE data latency in terms of number of clock cycles.
0168
0169 tWR-min-tck:
0170 $ref: /schemas/types.yaml#/definitions/uint32
0171 maximum: 15
0172 description: |
0173 WRITE recovery time in terms of number of clock cycles.
0174
0175 tWTR-min-tck:
0176 $ref: /schemas/types.yaml#/definitions/uint32
0177 maximum: 15
0178 description: |
0179 Internal WRITE-to-READ command delay in terms of number of clock cycles.
0180
0181 tXP-min-tck:
0182 $ref: /schemas/types.yaml#/definitions/uint32
0183 maximum: 255
0184 description: |
0185 Exit power-down to next valid command delay in terms of number of clock
0186 cycles.
0187
0188 tXSR-min-tck:
0189 $ref: /schemas/types.yaml#/definitions/uint32
0190 maximum: 1023
0191 description: |
0192 SELF REFRESH exit to next valid command delay in terms of number of clock
0193 cycles.
0194
0195 patternProperties:
0196 "^timings((-[0-9])+|(@[0-9a-f]+))?$":
0197 $ref: jedec,lpddr3-timings.yaml
0198 description: |
0199 The lpddr3 node may have one or more child nodes with timings.
0200 Each timing node provides AC timing parameters of the device for a given
0201 speed-bin. The user may provide the timings for as many speed-bins as is
0202 required.
0203
0204 required:
0205 - compatible
0206 - density
0207 - io-width
0208
0209 additionalProperties: false
0210
0211 examples:
0212 - |
0213 lpddr3 {
0214 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
0215 density = <16384>;
0216 io-width = <32>;
0217
0218 tCKE-min-tck = <2>;
0219 tCKESR-min-tck = <2>;
0220 tDQSCK-min-tck = <5>;
0221 tFAW-min-tck = <5>;
0222 tMRD-min-tck = <5>;
0223 tR2R-C2C-min-tck = <0>;
0224 tRAS-min-tck = <5>;
0225 tRC-min-tck = <6>;
0226 tRCD-min-tck = <3>;
0227 tRFC-min-tck = <17>;
0228 tRL-min-tck = <14>;
0229 tRPab-min-tck = <2>;
0230 tRPpb-min-tck = <2>;
0231 tRRD-min-tck = <2>;
0232 tRTP-min-tck = <2>;
0233 tW2W-C2C-min-tck = <0>;
0234 tWL-min-tck = <8>;
0235 tWR-min-tck = <7>;
0236 tWTR-min-tck = <2>;
0237 tXP-min-tck = <2>;
0238 tXSR-min-tck = <12>;
0239
0240 timings {
0241 compatible = "jedec,lpddr3-timings";
0242 max-freq = <800000000>;
0243 min-freq = <100000000>;
0244 tCKE = <3750>;
0245 tCKESR = <3750>;
0246 tFAW = <25000>;
0247 tMRD = <7000>;
0248 tR2R-C2C = <0>;
0249 tRAS = <23000>;
0250 tRC = <33750>;
0251 tRCD = <10000>;
0252 tRFC = <65000>;
0253 tRPab = <12000>;
0254 tRPpb = <12000>;
0255 tRRD = <6000>;
0256 tRTP = <3750>;
0257 tW2W-C2C = <0>;
0258 tWR = <7500>;
0259 tWTR = <3750>;
0260 tXP = <3750>;
0261 tXSR = <70000>;
0262 };
0263 };
