0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 properties:
0013 compatible:
0014 const: jedec,lpddr3-timings
0015
0016 reg:
0017 maxItems: 1
0018 description: |
0019 Maximum DDR clock frequency for the speed-bin, in Hz.
0020 Property is deprecated, use max-freq.
0021 deprecated: true
0022
0023 max-freq:
0024 $ref: /schemas/types.yaml#/definitions/uint32
0025 description: |
0026 Maximum DDR clock frequency for the speed-bin, in Hz.
0027
0028 min-freq:
0029 $ref: /schemas/types.yaml#/definitions/uint32
0030 description: |
0031 Minimum DDR clock frequency for the speed-bin, in Hz.
0032
0033 tCKE:
0034 $ref: /schemas/types.yaml#/definitions/uint32
0035 description: |
0036 CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
0037
0038 tCKESR:
0039 $ref: /schemas/types.yaml#/definitions/uint32
0040 description: |
0041 CKE minimum pulse width during SELF REFRESH (low pulse width during
0042 SELF REFRESH) in pico seconds.
0043
0044 tFAW:
0045 $ref: /schemas/types.yaml#/definitions/uint32
0046 description: |
0047 Four-bank activate window in pico seconds.
0048
0049 tMRD:
0050 $ref: /schemas/types.yaml#/definitions/uint32
0051 description: |
0052 Mode register set command delay in pico seconds.
0053
0054 tR2R-C2C:
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 description: |
0057 Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
0058
0059 tRAS:
0060 $ref: /schemas/types.yaml#/definitions/uint32
0061 description: |
0062 Row active time in pico seconds.
0063
0064 tRC:
0065 $ref: /schemas/types.yaml#/definitions/uint32
0066 description: |
0067 ACTIVATE-to-ACTIVATE command period in pico seconds.
0068
0069 tRCD:
0070 $ref: /schemas/types.yaml#/definitions/uint32
0071 description: |
0072 RAS-to-CAS delay in pico seconds.
0073
0074 tRFC:
0075 $ref: /schemas/types.yaml#/definitions/uint32
0076 description: |
0077 Refresh Cycle time in pico seconds.
0078
0079 tRPab:
0080 $ref: /schemas/types.yaml#/definitions/uint32
0081 description: |
0082 Row precharge time (all banks) in pico seconds.
0083
0084 tRPpb:
0085 $ref: /schemas/types.yaml#/definitions/uint32
0086 description: |
0087 Row precharge time (single banks) in pico seconds.
0088
0089 tRRD:
0090 $ref: /schemas/types.yaml#/definitions/uint32
0091 description: |
0092 Active bank A to active bank B in pico seconds.
0093
0094 tRTP:
0095 $ref: /schemas/types.yaml#/definitions/uint32
0096 description: |
0097 Internal READ to PRECHARGE command delay in pico seconds.
0098
0099 tW2W-C2C:
0100 $ref: /schemas/types.yaml#/definitions/uint32
0101 description: |
0102 Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
0103
0104 tWR:
0105 $ref: /schemas/types.yaml#/definitions/uint32
0106 description: |
0107 WRITE recovery time in pico seconds.
0108
0109 tWTR:
0110 $ref: /schemas/types.yaml#/definitions/uint32
0111 description: |
0112 Internal WRITE-to-READ command delay in pico seconds.
0113
0114 tXP:
0115 $ref: /schemas/types.yaml#/definitions/uint32
0116 description: |
0117 Exit power-down to next valid command delay in pico seconds.
0118
0119 tXSR:
0120 $ref: /schemas/types.yaml#/definitions/uint32
0121 description: |
0122 SELF REFRESH exit to next valid command delay in pico seconds.
0123
0124 required:
0125 - compatible
0126 - min-freq
0127 - max-freq
0128
0129 additionalProperties: false
0130
0131 examples:
0132 - |
0133 lpddr3 {
0134 timings {
0135 compatible = "jedec,lpddr3-timings";
0136 max-freq = <800000000>;
0137 min-freq = <100000000>;
0138 tCKE = <3750>;
0139 tCKESR = <3750>;
0140 tFAW = <25000>;
0141 tMRD = <7000>;
0142 tR2R-C2C = <0>;
0143 tRAS = <23000>;
0144 tRC = <33750>;
0145 tRCD = <10000>;
0146 tRFC = <65000>;
0147 tRPab = <12000>;
0148 tRPpb = <12000>;
0149 tRRD = <6000>;
0150 tRTP = <3750>;
0151 tW2W-C2C = <0>;
0152 tWR = <7500>;
0153 tWTR = <3750>;
0154 tXP = <3750>;
0155 tXSR = <70000>;
0156 };
0157 };
