0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 properties:
0013 compatible:
0014 oneOf:
0015 - items:
0016 - enum:
0017 - elpida,ECB240ABACN
0018 - elpida,B8132B2PB-6D-F
0019 - enum:
0020 - jedec,lpddr2-s4
0021 - items:
0022 - enum:
0023 - jedec,lpddr2-s2
0024 - items:
0025 - enum:
0026 - jedec,lpddr2-nvm
0027
0028 revision-id1:
0029 $ref: /schemas/types.yaml#/definitions/uint32
0030 maximum: 255
0031 description: |
0032 Revision 1 value of SDRAM chip. Obtained from device datasheet.
0033 Property is deprecated, use revision-id instead.
0034 deprecated: true
0035
0036 revision-id2:
0037 $ref: /schemas/types.yaml#/definitions/uint32
0038 maximum: 255
0039 description: |
0040 Revision 2 value of SDRAM chip. Obtained from device datasheet.
0041 Property is deprecated, use revision-id instead.
0042 deprecated: true
0043
0044 revision-id:
0045 $ref: /schemas/types.yaml#/definitions/uint32-array
0046 description: |
0047 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
0048 minItems: 2
0049 maxItems: 2
0050 items:
0051 minimum: 0
0052 maximum: 255
0053
0054 density:
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 description: |
0057 Density in megabits of SDRAM chip. Obtained from device datasheet.
0058 enum:
0059 - 64
0060 - 128
0061 - 256
0062 - 512
0063 - 1024
0064 - 2048
0065 - 4096
0066 - 8192
0067 - 16384
0068 - 32768
0069
0070 io-width:
0071 $ref: /schemas/types.yaml#/definitions/uint32
0072 description: |
0073 IO bus width in bits of SDRAM chip. Obtained from device datasheet.
0074 enum:
0075 - 32
0076 - 16
0077 - 8
0078
0079 tRRD-min-tck:
0080 $ref: /schemas/types.yaml#/definitions/uint32
0081 maximum: 16
0082 description: |
0083 Active bank a to active bank b in terms of number of clock cycles.
0084 Obtained from device datasheet.
0085
0086 tWTR-min-tck:
0087 $ref: /schemas/types.yaml#/definitions/uint32
0088 maximum: 16
0089 description: |
0090 Internal WRITE-to-READ command delay in terms of number of clock cycles.
0091 Obtained from device datasheet.
0092
0093 tXP-min-tck:
0094 $ref: /schemas/types.yaml#/definitions/uint32
0095 maximum: 16
0096 description: |
0097 Exit power-down to next valid command delay in terms of number of clock
0098 cycles. Obtained from device datasheet.
0099
0100 tRTP-min-tck:
0101 $ref: /schemas/types.yaml#/definitions/uint32
0102 maximum: 16
0103 description: |
0104 Internal READ to PRECHARGE command delay in terms of number of clock
0105 cycles. Obtained from device datasheet.
0106
0107 tCKE-min-tck:
0108 $ref: /schemas/types.yaml#/definitions/uint32
0109 maximum: 16
0110 description: |
0111 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
0112 of clock cycles. Obtained from device datasheet.
0113
0114 tRPab-min-tck:
0115 $ref: /schemas/types.yaml#/definitions/uint32
0116 maximum: 16
0117 description: |
0118 Row precharge time (all banks) in terms of number of clock cycles.
0119 Obtained from device datasheet.
0120
0121 tRCD-min-tck:
0122 $ref: /schemas/types.yaml#/definitions/uint32
0123 maximum: 16
0124 description: |
0125 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
0126 device datasheet.
0127
0128 tWR-min-tck:
0129 $ref: /schemas/types.yaml#/definitions/uint32
0130 maximum: 16
0131 description: |
0132 WRITE recovery time in terms of number of clock cycles. Obtained from
0133 device datasheet.
0134
0135 tRASmin-min-tck:
0136 $ref: /schemas/types.yaml#/definitions/uint32
0137 maximum: 16
0138 description: |
0139 Row active time in terms of number of clock cycles. Obtained from device
0140 datasheet.
0141
0142 tCKESR-min-tck:
0143 $ref: /schemas/types.yaml#/definitions/uint32
0144 maximum: 16
0145 description: |
0146 CKE minimum pulse width during SELF REFRESH (low pulse width during
0147 SELF REFRESH) in terms of number of clock cycles. Obtained from device
0148 datasheet.
0149
0150 tFAW-min-tck:
0151 $ref: /schemas/types.yaml#/definitions/uint32
0152 maximum: 16
0153 description: |
0154 Four-bank activate window in terms of number of clock cycles. Obtained
0155 from device datasheet.
0156
0157 patternProperties:
0158 "^lpddr2-timings":
0159 $ref: jedec,lpddr2-timings.yaml
0160 description: |
0161 The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
0162 "lpddr2-timings" provides AC timing parameters of the device for
0163 a given speed-bin. The user may provide the timings for as many
0164 speed-bins as is required.
0165
0166 required:
0167 - compatible
0168 - density
0169 - io-width
0170
0171 additionalProperties: false
0172
0173 examples:
0174 - |
0175 elpida_ECB240ABACN: lpddr2 {
0176 compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
0177 density = <2048>;
0178 io-width = <32>;
0179 revision-id = <1 0>;
0180
0181 tRPab-min-tck = <3>;
0182 tRCD-min-tck = <3>;
0183 tWR-min-tck = <3>;
0184 tRASmin-min-tck = <3>;
0185 tRRD-min-tck = <2>;
0186 tWTR-min-tck = <2>;
0187 tXP-min-tck = <2>;
0188 tRTP-min-tck = <2>;
0189 tCKE-min-tck = <3>;
0190 tCKESR-min-tck = <3>;
0191 tFAW-min-tck = <8>;
0192
0193 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
0194 compatible = "jedec,lpddr2-timings";
0195 min-freq = <10000000>;
0196 max-freq = <400000000>;
0197 tRPab = <21000>;
0198 tRCD = <18000>;
0199 tWR = <15000>;
0200 tRAS-min = <42000>;
0201 tRRD = <10000>;
0202 tWTR = <7500>;
0203 tXP = <7500>;
0204 tRTP = <7500>;
0205 tCKESR = <15000>;
0206 tDQSCK-max = <5500>;
0207 tFAW = <50000>;
0208 tZQCS = <90000>;
0209 tZQCL = <360000>;
0210 tZQinit = <1000000>;
0211 tRAS-max-ns = <70000>;
0212 };
0213
0214 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
0215 compatible = "jedec,lpddr2-timings";
0216 min-freq = <10000000>;
0217 max-freq = <200000000>;
0218 tRPab = <21000>;
0219 tRCD = <18000>;
0220 tWR = <15000>;
0221 tRAS-min = <42000>;
0222 tRRD = <10000>;
0223 tWTR = <10000>;
0224 tXP = <7500>;
0225 tRTP = <7500>;
0226 tCKESR = <15000>;
0227 tDQSCK-max = <5500>;
0228 tFAW = <50000>;
0229 tZQCS = <90000>;
0230 tZQCL = <360000>;
0231 tZQinit = <1000000>;
0232 tRAS-max-ns = <70000>;
0233 };
0234 };
