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OSCL-LXR

 
 

    


0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
0008 
0009 maintainers:
0010   - Krzysztof Kozlowski <krzk@kernel.org>
0011 
0012 properties:
0013   compatible:
0014     const: jedec,lpddr2-timings
0015 
0016   max-freq:
0017     $ref: /schemas/types.yaml#/definitions/uint32
0018     description: |
0019       Maximum DDR clock frequency for the speed-bin, in Hz.
0020 
0021   min-freq:
0022     $ref: /schemas/types.yaml#/definitions/uint32
0023     description: |
0024       Minimum DDR clock frequency for the speed-bin, in Hz.
0025 
0026   tCKESR:
0027     $ref: /schemas/types.yaml#/definitions/uint32
0028     description: |
0029       CKE minimum pulse width during SELF REFRESH (low pulse width during
0030       SELF REFRESH) in pico seconds.
0031 
0032   tDQSCK-max:
0033     $ref: /schemas/types.yaml#/definitions/uint32
0034     description: |
0035       DQS output data access time from CK_t/CK_c in pico seconds.
0036 
0037   tDQSCK-max-derated:
0038     $ref: /schemas/types.yaml#/definitions/uint32
0039     description: |
0040       DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
0041       seconds.
0042 
0043   tFAW:
0044     $ref: /schemas/types.yaml#/definitions/uint32
0045     description: |
0046       Four-bank activate window in pico seconds.
0047 
0048   tRAS-max-ns:
0049     description: |
0050       Row active time in nano seconds.
0051 
0052   tRAS-min:
0053     $ref: /schemas/types.yaml#/definitions/uint32
0054     description: |
0055       Row active time in pico seconds.
0056 
0057   tRCD:
0058     $ref: /schemas/types.yaml#/definitions/uint32
0059     description: |
0060       RAS-to-CAS delay in pico seconds.
0061 
0062   tRPab:
0063     $ref: /schemas/types.yaml#/definitions/uint32
0064     description: |
0065       Row precharge time (all banks) in pico seconds.
0066 
0067   tRRD:
0068     $ref: /schemas/types.yaml#/definitions/uint32
0069     description: |
0070       Active bank A to active bank B in pico seconds.
0071 
0072   tRTP:
0073     $ref: /schemas/types.yaml#/definitions/uint32
0074     description: |
0075       Internal READ to PRECHARGE command delay in pico seconds.
0076 
0077   tWR:
0078     $ref: /schemas/types.yaml#/definitions/uint32
0079     description: |
0080       WRITE recovery time in pico seconds.
0081 
0082   tWTR:
0083     $ref: /schemas/types.yaml#/definitions/uint32
0084     description: |
0085       Internal WRITE-to-READ command delay in pico seconds.
0086 
0087   tXP:
0088     $ref: /schemas/types.yaml#/definitions/uint32
0089     description: |
0090       Exit power-down to next valid command delay in pico seconds.
0091 
0092   tZQCL:
0093     $ref: /schemas/types.yaml#/definitions/uint32
0094     description: |
0095       Long calibration time in pico seconds.
0096 
0097   tZQCS:
0098     $ref: /schemas/types.yaml#/definitions/uint32
0099     description: |
0100       Short calibration time in pico seconds.
0101 
0102   tZQinit:
0103     $ref: /schemas/types.yaml#/definitions/uint32
0104     description: |
0105       Initialization calibration time in pico seconds.
0106 
0107 required:
0108   - compatible
0109   - min-freq
0110   - max-freq
0111 
0112 additionalProperties: false
0113 
0114 examples:
0115   - |
0116     timings {
0117         compatible = "jedec,lpddr2-timings";
0118         min-freq = <10000000>;
0119         max-freq = <400000000>;
0120         tCKESR = <15000>;
0121         tDQSCK-max = <5500>;
0122         tFAW = <50000>;
0123         tRAS-max-ns = <70000>;
0124         tRAS-min = <42000>;
0125         tRPab = <21000>;
0126         tRCD = <18000>;
0127         tRRD = <10000>;
0128         tRTP = <7500>;
0129         tWR = <15000>;
0130         tWTR = <7500>;
0131         tXP = <7500>;
0132         tZQCL = <360000>;
0133         tZQCS = <90000>;
0134         tZQinit = <1000000>;
0135     };