bindings/memory-controllers/calxeda-ddr-ctrlr.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Calxeda DDR memory controller binding
0008
0009 description: |
0010   The Calxeda DDR memory controller is initialised and programmed by the
0011   firmware, but an OS might want to read its registers for error reporting
0012   purposes and to learn about the DRAM topology.
0013
0014 maintainers:
0015   - Andre Przywara <andre.przywara@arm.com>
0016
0017 properties:
0018   compatible:
0019     enum:
0020       - calxeda,hb-ddr-ctrl
0021       - calxeda,ecx-2000-ddr-ctrl
0022
0023   reg:
0024     maxItems: 1
0025
0026   interrupts:
0027     maxItems: 1
0028
0029 required:
0030   - compatible
0031   - reg
0032   - interrupts
0033
0034 additionalProperties: false
0035
0036 examples:
0037   - |
0038     memory-controller@fff00000 {
0039         compatible = "calxeda,hb-ddr-ctrl";
0040         reg = <0xfff00000 0x1000>;
0041         interrupts = <0 91 4>;
0042     };