0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Baikal-T1 L2-cache Control Block
0009
0010 maintainers:
0011 - Serge Semin <fancer.lancer@gmail.com>
0012
0013 description: |
0014 By means of the System Controller Baikal-T1 SoC exposes a few settings to
0015 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
0016 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
0017 L2-cache controller block is responsible for the tuning. Its DT node is
0018 supposed to be a child of the system controller.
0019
0020 properties:
0021 compatible:
0022 const: baikal,bt1-l2-ctl
0023
0024 reg:
0025 maxItems: 1
0026
0027 baikal,l2-ws-latency:
0028 $ref: /schemas/types.yaml#/definitions/uint32
0029 description: Cycles of latency for Way-select RAM accesses
0030 default: 0
0031 minimum: 0
0032 maximum: 3
0033
0034 baikal,l2-tag-latency:
0035 $ref: /schemas/types.yaml#/definitions/uint32
0036 description: Cycles of latency for Tag RAM accesses
0037 default: 0
0038 minimum: 0
0039 maximum: 3
0040
0041 baikal,l2-data-latency:
0042 $ref: /schemas/types.yaml#/definitions/uint32
0043 description: Cycles of latency for Data RAM accesses
0044 default: 1
0045 minimum: 0
0046 maximum: 3
0047
0048 additionalProperties: false
0049
0050 required:
0051 - compatible
0052
0053 examples:
0054 - |
0055 l2@1f04d028 {
0056 compatible = "baikal,bt1-l2-ctl";
0057 reg = <0x1f04d028 0x004>;
0058
0059 baikal,l2-ws-latency = <1>;
0060 baikal,l2-tag-latency = <1>;
0061 baikal,l2-data-latency = <2>;
0062 };
0063 ...
