bindings/memory-controllers/arm%2Cpl353-smc.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
0008
0009 maintainers:
0010   - Miquel Raynal <miquel.raynal@bootlin.com>
0011   - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
0012
0013 description:
0014   The PL353 Static Memory Controller is a bus where you can connect two kinds
0015   of memory interfaces, which are NAND and memory mapped interfaces (such as
0016   SRAM or NOR).
0017
0018 # We need a select here so we don't match all nodes with 'arm,primecell'
0019 select:
0020   properties:
0021     compatible:
0022       contains:
0023         const: arm,pl353-smc-r2p1
0024   required:
0025     - compatible
0026
0027 properties:
0028   $nodename:
0029     pattern: "^memory-controller@[0-9a-f]+$"
0030
0031   compatible:
0032     items:
0033       - const: arm,pl353-smc-r2p1
0034       - const: arm,primecell
0035
0036   "#address-cells":
0037     const: 2
0038
0039   "#size-cells":
0040     const: 1
0041
0042   reg:
0043     items:
0044       - description:
0045           Configuration registers for the host and sub-controllers.
0046           The three chip select regions are defined in 'ranges'.
0047
0048   clocks:
0049     items:
0050       - description: clock for the memory device bus
0051       - description: main clock of the SMC
0052
0053   clock-names:
0054     items:
0055       - const: memclk
0056       - const: apb_pclk
0057
0058   ranges:
0059     minItems: 1
0060     description: |
0061       Memory bus areas for interacting with the devices. Reflects
0062       the memory layout with four integer values following:
0063       <cs-number> 0 <offset> <size>
0064     items:
0065       - description: NAND bank 0
0066       - description: NOR/SRAM bank 0
0067       - description: NOR/SRAM bank 1
0068
0069   interrupts: true
0070
0071 patternProperties:
0072   "@[0-3],[a-f0-9]+$":
0073     type: object
0074     description: |
0075       The child device node represents the controller connected to the SMC
0076       bus. The controller can be a NAND controller or a pair of any memory
0077       mapped controllers such as NOR and SRAM controllers.
0078
0079     properties:
0080       compatible:
0081         description:
0082           Compatible of memory controller.
0083
0084       reg:
0085         items:
0086           - items:
0087               - description: |
0088                   Chip-select ID, as in the parent range property.
0089                 minimum: 0
0090                 maximum: 2
0091               - description: |
0092                   Offset of the memory region requested by the device.
0093               - description: |
0094                   Length of the memory region requested by the device.
0095
0096     required:
0097       - compatible
0098       - reg
0099
0100 required:
0101   - compatible
0102   - reg
0103   - clock-names
0104   - clocks
0105   - "#address-cells"
0106   - "#size-cells"
0107   - ranges
0108
0109 additionalProperties: false
0110
0111 examples:
0112   - |
0113     smcc: memory-controller@e000e000 {
0114       compatible = "arm,pl353-smc-r2p1", "arm,primecell";
0115       reg = <0xe000e000 0x0001000>;
0116       clock-names = "memclk", "apb_pclk";
0117       clocks = <&clkc 11>, <&clkc 44>;
0118       ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0119                 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0120                 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
0121       #address-cells = <2>;
0122       #size-cells = <1>;
0123
0124       nfc0: nand-controller@0,0 {
0125         compatible = "arm,pl353-nand-r2p1";
0126         reg = <0 0 0x1000000>;
0127         #address-cells = <1>;
0128         #size-cells = <0>;
0129       };
0130     };