0001 * Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
0002
0003 Required properties:
0004
0005 - compatible: Must be "arm,primecell" and exactly one from
0006 "arm,pl172", "arm,pl175" or "arm,pl176".
0007
0008 - reg: Must contains offset/length value for controller.
0009
0010 - #address-cells: Must be 2. The partition number has to be encoded in the
0011 first address cell and it may accept values 0..N-1
0012 (N - total number of partitions). The second cell is the
0013 offset into the partition.
0014
0015 - #size-cells: Must be set to 1.
0016
0017 - ranges: Must contain one or more chip select memory regions.
0018
0019 - clocks: Must contain references to controller clocks.
0020
0021 - clock-names: Must contain "mpmcclk" and "apb_pclk".
0022
0023 - clock-ranges: Empty property indicating that child nodes can inherit
0024 named clocks. Required only if clock tree data present
0025 in device tree.
0026 See clock-bindings.txt
0027
0028 Child chip-select (cs) nodes contain the memory devices nodes connected to
0029 such as NOR (e.g. cfi-flash) and NAND.
0030
0031 Required child cs node properties:
0032
0033 - #address-cells: Must be 2.
0034
0035 - #size-cells: Must be 1.
0036
0037 - ranges: Empty property indicating that child nodes can inherit
0038 memory layout.
0039
0040 - clock-ranges: Empty property indicating that child nodes can inherit
0041 named clocks. Required only if clock tree data present
0042 in device tree.
0043
0044 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
0045 which chipselect is used for accessing the memory.
0046
0047 - mpmc,memory-width: Width of the chip select memory. Must be equal to
0048 either 8, 16 or 32.
0049
0050 Optional child cs node config properties:
0051
0052 - mpmc,async-page-mode: Enable asynchronous page mode.
0053
0054 - mpmc,cs-active-high: Set chip select polarity to active high.
0055
0056 - mpmc,byte-lane-low: Set byte lane state to low.
0057
0058 - mpmc,extended-wait: Enable extended wait.
0059
0060 - mpmc,buffer-enable: Enable write buffer, option is not supported by
0061 PL175 and PL176 controllers.
0062
0063 - mpmc,write-protect: Enable write protect.
0064
0065 Optional child cs node timing properties:
0066
0067 - mpmc,write-enable-delay: Delay from chip select assertion to write
0068 enable (WE signal) in nano seconds.
0069
0070 - mpmc,output-enable-delay: Delay from chip select assertion to output
0071 enable (OE signal) in nano seconds.
0072
0073 - mpmc,write-access-delay: Delay from chip select assertion to write
0074 access in nano seconds.
0075
0076 - mpmc,read-access-delay: Delay from chip select assertion to read
0077 access in nano seconds.
0078
0079 - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
0080 accesses in nano seconds.
0081
0082 - mpmc,turn-round-delay: Delay between access to memory banks in nano
0083 seconds.
0084
0085 If any of the above timing parameters are absent, current parameter value will
0086 be taken from the corresponding HW reg.
0087
0088 Example for pl172 with nor flash on chip select 0 shown below.
0089
0090 emc: memory-controller@40005000 {
0091 compatible = "arm,pl172", "arm,primecell";
0092 reg = <0x40005000 0x1000>;
0093 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
0094 clock-names = "mpmcclk", "apb_pclk";
0095 #address-cells = <2>;
0096 #size-cells = <1>;
0097 ranges = <0 0 0x1c000000 0x1000000
0098 1 0 0x1d000000 0x1000000
0099 2 0 0x1e000000 0x1000000
0100 3 0 0x1f000000 0x1000000>;
0101
0102 cs0 {
0103 #address-cells = <2>;
0104 #size-cells = <1>;
0105 ranges;
0106
0107 mpmc,cs = <0>;
0108 mpmc,memory-width = <16>;
0109 mpmc,byte-lane-low;
0110 mpmc,write-enable-delay = <0>;
0111 mpmc,output-enable-delay = <0>;
0112 mpmc,read-enable-delay = <70>;
0113 mpmc,page-mode-read-delay = <70>;
0114
0115 flash@0,0 {
0116 compatible = "sst,sst39vf320", "cfi-flash";
0117 reg = <0 0 0x400000>;
0118 bank-width = <2>;
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 partition@0 {
0122 label = "data";
0123 reg = <0 0x400000>;
0124 };
0125 };
0126 };
0127 };
