0001 Xilinx Video IP Pipeline (VIPP)
0002 -------------------------------
0003
0004 General concept
0005 ---------------
0006
0007 Xilinx video IP pipeline processes video streams through one or more Xilinx
0008 video IP cores. Each video IP core is represented as documented in video.txt
0009 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
0010 node of the VIPP represents as a top level node of the pipeline and defines
0011 mappings between DMAs and the video IP cores.
0012
0013 Required properties:
0014
0015 - compatible: Must be "xlnx,video".
0016
0017 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
0018 in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
0019 requires a DMA channel with the identifier string set to "port" followed by
0020 the port index.
0021
0022 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
0023
0024 Required port properties:
0025
0026 - direction: should be either "input" or "output" depending on the direction
0027 of stream.
0028
0029 Example:
0030
0031 video_cap {
0032 compatible = "xlnx,video";
0033 dmas = <&vdma_1 1>, <&vdma_3 1>;
0034 dma-names = "port0", "port1";
0035
0036 ports {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 port@0 {
0041 reg = <0>;
0042 direction = "input";
0043 vcap0_in0: endpoint {
0044 remote-endpoint = <&scaler0_out>;
0045 };
0046 };
0047 port@1 {
0048 reg = <1>;
0049 direction = "input";
0050 vcap0_in1: endpoint {
0051 remote-endpoint = <&switch_out1>;
0052 };
0053 };
0054 };
0055 };
