0001 Xilinx Video Test Pattern Generator (TPG)
0002 -----------------------------------------
0003
0004 Required properties:
0005
0006 - compatible: Must contain at least one of
0007
0008 "xlnx,v-tpg-5.0" (TPG version 5.0)
0009 "xlnx,v-tpg-6.0" (TPG version 6.0)
0010
0011 TPG versions backward-compatible with previous versions should list all
0012 compatible versions in the newer to older order.
0013
0014 - reg: Physical base address and length of the registers set for the device.
0015
0016 - clocks: Reference to the video core clock.
0017
0018 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
0019 video.txt.
0020
0021 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
0022 The TPG has a single output port numbered 0.
0023
0024 Optional properties:
0025
0026 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
0027 video timings for the TPG test patterns.
0028
0029 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
0030 input. The GPIO active level corresponds to the selection of VTC-generated
0031 video timings.
0032
0033 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
0034 synthesized with two ports and forbidden when synthesized with one port.
0035
0036 Example:
0037
0038 tpg_0: tpg@40050000 {
0039 compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
0040 reg = <0x40050000 0x10000>;
0041 clocks = <&clkc 15>;
0042
0043 xlnx,vtc = <&vtc_3>;
0044 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
0045
0046 ports {
0047 #address-cells = <1>;
0048 #size-cells = <0>;
0049
0050 port@0 {
0051 reg = <0>;
0052
0053 xlnx,video-format = <XVIP_VF_YUV_422>;
0054 xlnx,video-width = <8>;
0055
0056 tpg_in: endpoint {
0057 remote-endpoint = <&adv7611_out>;
0058 };
0059 };
0060 port@1 {
0061 reg = <1>;
0062
0063 xlnx,video-format = <XVIP_VF_YUV_422>;
0064 xlnx,video-width = <8>;
0065
0066 tpg1_out: endpoint {
0067 remote-endpoint = <&switch_in0>;
0068 };
0069 };
0070 };
0071 };
