0001 DT bindings for Xilinx video IP cores
0002 -------------------------------------
0003
0004 Xilinx video IP cores process video streams by acting as video sinks and/or
0005 sources. They are connected by links through their input and output ports,
0006 creating a video pipeline.
0007
0008 Each video IP core is represented by an AMBA bus child node in the device
0009 tree using bindings documented in this directory. Connections between the IP
0010 cores are represented as defined in ../video-interfaces.txt.
0011
0012 The whole pipeline is represented by an AMBA bus child node in the device
0013 tree using bindings documented in ./xlnx,video.txt.
0014
0015 Common properties
0016 -----------------
0017
0018 The following properties are common to all Xilinx video IP cores.
0019
0020 - xlnx,video-format: This property represents a video format transmitted on an
0021 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
0022 Video IP and System Design Guide" [UG934]. How the format relates to the IP
0023 core is described in the IP core bindings documentation.
0024
0025 - xlnx,video-width: This property qualifies the video format with the sample
0026 width expressed as a number of bits per pixel component. All components must
0027 use the same width.
0028
0029 - xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property
0030 describes the sensor's color filter array pattern. Supported values are
0031 "bggr", "gbrg", "grbg", "rggb" and "mono". If not specified, the pattern
0032 defaults to "mono".
0033
0034
0035 [UG934] https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf
