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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Common bindings for video receiver and transmitter interface endpoints
0008 
0009 maintainers:
0010   - Sakari Ailus <sakari.ailus@linux.intel.com>
0011   - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0012 
0013 description: |
0014   Video data pipelines usually consist of external devices, e.g. camera sensors,
0015   controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
0016   video DMA engines and video data processors.
0017 
0018   SoC internal blocks are described by DT nodes, placed similarly to other SoC
0019   blocks.  External devices are represented as child nodes of their respective
0020   bus controller nodes, e.g. I2C.
0021 
0022   Data interfaces on all video devices are described by their child 'port' nodes.
0023   Configuration of a port depends on other devices participating in the data
0024   transfer and is described by 'endpoint' subnodes.
0025 
0026   device {
0027       ...
0028       ports {
0029           #address-cells = <1>;
0030           #size-cells = <0>;
0031 
0032           port@0 {
0033               ...
0034               endpoint@0 { ... };
0035               endpoint@1 { ... };
0036           };
0037           port@1 { ... };
0038       };
0039   };
0040 
0041   If a port can be configured to work with more than one remote device on the same
0042   bus, an 'endpoint' child node must be provided for each of them.  If more than
0043   one port is present in a device node or there is more than one endpoint at a
0044   port, or port node needs to be associated with a selected hardware interface,
0045   a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
0046   used.
0047 
0048   All 'port' nodes can be grouped under optional 'ports' node, which allows to
0049   specify #address-cells, #size-cells properties independently for the 'port'
0050   and 'endpoint' nodes and any child device nodes a device might have.
0051 
0052   Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
0053   phandles.  An endpoint subnode of a device contains all properties needed for
0054   configuration of this device for data exchange with other device.  In most
0055   cases properties at the peer 'endpoint' nodes will be identical, however they
0056   might need to be different when there is any signal modifications on the bus
0057   between two devices, e.g. there are logic signal inverters on the lines.
0058 
0059   It is allowed for multiple endpoints at a port to be active simultaneously,
0060   where supported by a device.  For example, in case where a data interface of
0061   a device is partitioned into multiple data busses, e.g. 16-bit input port
0062   divided into two separate ITU-R BT.656 8-bit busses.  In such case bus-width
0063   and data-shift properties can be used to assign physical data lines to each
0064   endpoint node (logical bus).
0065 
0066   Documenting bindings for devices
0067   --------------------------------
0068 
0069   All required and optional bindings the device supports shall be explicitly
0070   documented in device DT binding documentation. This also includes port and
0071   endpoint nodes for the device, including unit-addresses and reg properties
0072   where relevant.
0073 
0074 allOf:
0075   - $ref: /schemas/graph.yaml#/$defs/endpoint-base
0076 
0077 properties:
0078   slave-mode:
0079     type: boolean
0080     description:
0081       Indicates that the link is run in slave mode. The default when this
0082       property is not specified is master mode. In the slave mode horizontal and
0083       vertical synchronization signals are provided to the slave device (data
0084       source) by the master device (data sink). In the master mode the data
0085       source device is also the source of the synchronization signals.
0086 
0087   bus-type:
0088     $ref: /schemas/types.yaml#/definitions/uint32
0089     enum:
0090       - 1 # MIPI CSI-2 C-PHY
0091       - 2 # MIPI CSI1
0092       - 3 # CCP2
0093       - 4 # MIPI CSI-2 D-PHY
0094       - 5 # Parallel
0095       - 6 # BT.656
0096       - 7 # DPI
0097     description:
0098       Data bus type.
0099 
0100   bus-width:
0101     $ref: /schemas/types.yaml#/definitions/uint32
0102     maximum: 64
0103     description:
0104       Number of data lines actively used, valid for the parallel busses.
0105 
0106   data-shift:
0107     $ref: /schemas/types.yaml#/definitions/uint32
0108     maximum: 64
0109     description:
0110       On the parallel data busses, if bus-width is used to specify the number of
0111       data lines, data-shift can be used to specify which data lines are used,
0112       e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
0113 
0114   hsync-active:
0115     $ref: /schemas/types.yaml#/definitions/uint32
0116     enum: [ 0, 1 ]
0117     description:
0118       Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
0119 
0120   vsync-active:
0121     $ref: /schemas/types.yaml#/definitions/uint32
0122     enum: [ 0, 1 ]
0123     description:
0124       Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. Note,
0125       that if HSYNC and VSYNC polarities are not specified, embedded
0126       synchronization may be required, where supported.
0127 
0128   data-active:
0129     $ref: /schemas/types.yaml#/definitions/uint32
0130     enum: [ 0, 1 ]
0131     description:
0132       Similar to HSYNC and VSYNC, specifies data line polarity.
0133 
0134   data-enable-active:
0135     $ref: /schemas/types.yaml#/definitions/uint32
0136     enum: [ 0, 1 ]
0137     description:
0138       Similar to HSYNC and VSYNC, specifies the data enable signal polarity.
0139 
0140   field-even-active:
0141     $ref: /schemas/types.yaml#/definitions/uint32
0142     enum: [ 0, 1 ]
0143     description:
0144       Field signal level during the even field data transmission.
0145 
0146   pclk-sample:
0147     $ref: /schemas/types.yaml#/definitions/uint32
0148     enum: [ 0, 1 ]
0149     description:
0150       Sample data on rising (1) or falling (0) edge of the pixel clock signal.
0151 
0152   sync-on-green-active:
0153     $ref: /schemas/types.yaml#/definitions/uint32
0154     enum: [ 0, 1 ]
0155     description:
0156       Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively.
0157 
0158   data-lanes:
0159     $ref: /schemas/types.yaml#/definitions/uint32-array
0160     minItems: 1
0161     maxItems: 8
0162     items:
0163       # Assume up to 9 physical lane indices
0164       maximum: 8
0165     description:
0166       An array of physical data lane indexes. Position of an entry determines
0167       the logical lane number, while the value of an entry indicates physical
0168       lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
0169       assuming the clock lane is on hardware lane 0. If the hardware does not
0170       support lane reordering, monotonically incremented values shall be used
0171       from 0 or 1 onwards, depending on whether or not there is also a clock
0172       lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
0173 
0174   clock-lanes:
0175     $ref: /schemas/types.yaml#/definitions/uint32
0176     # Assume up to 9 physical lane indices
0177     maximum: 8
0178     description:
0179       Physical clock lane index. Position of an entry determines the logical
0180       lane number, while the value of an entry indicates physical lane, e.g. for
0181       a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
0182       clock lane on hardware lane 0. This property is valid for serial busses
0183       only (e.g. MIPI CSI-2).
0184 
0185   clock-noncontinuous:
0186     type: boolean
0187     description:
0188       Allow MIPI CSI-2 non-continuous clock mode.
0189 
0190   link-frequencies:
0191     $ref: /schemas/types.yaml#/definitions/uint64-array
0192     description:
0193       Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
0194       actual frequency of the bus, not bits per clock per lane value. An array
0195       of 64-bit unsigned integers.
0196 
0197   lane-polarities:
0198     $ref: /schemas/types.yaml#/definitions/uint32-array
0199     minItems: 1
0200     maxItems: 9
0201     items:
0202       enum: [ 0, 1 ]
0203     description:
0204       An array of polarities of the lanes starting from the clock lane and
0205       followed by the data lanes in the same order as in data-lanes. Valid
0206       values are 0 (normal) and 1 (inverted). The length of the array should be
0207       the combined length of data-lanes and clock-lanes properties. If the
0208       lane-polarities property is omitted, the value must be interpreted as 0
0209       (normal). This property is valid for serial busses only.
0210 
0211   strobe:
0212     $ref: /schemas/types.yaml#/definitions/uint32
0213     enum: [ 0, 1 ]
0214     description:
0215       Whether the clock signal is used as clock (0) or strobe (1). Used with
0216       CCP2, for instance.
0217 
0218 additionalProperties: true