0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/ti,cal.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings
0008
0009 maintainers:
0010 - Benoit Parrot <bparrot@ti.com>
0011
0012 description: |-
0013 The Camera Adaptation Layer (CAL) is a key component for image capture
0014 applications. The capture module provides the system interface and the
0015 processing capability to connect CSI2 image-sensor modules to the
0016 DRA72x device.
0017
0018 CAL supports 2 camera port nodes on MIPI bus.
0019
0020 properties:
0021 compatible:
0022 enum:
0023 # for DRA72 controllers
0024 - ti,dra72-cal
0025 # for DRA72 controllers pre ES2.0
0026 - ti,dra72-pre-es2-cal
0027 # for DRA76 controllers
0028 - ti,dra76-cal
0029 # for AM654 controllers
0030 - ti,am654-cal
0031
0032 reg:
0033 minItems: 2
0034 items:
0035 - description: The CAL main register region
0036 - description: The RX Core0 (DPHY0) register region
0037 - description: The RX Core1 (DPHY1) register region
0038
0039 reg-names:
0040 minItems: 2
0041 items:
0042 - const: cal_top
0043 - const: cal_rx_core0
0044 - const: cal_rx_core1
0045
0046 interrupts:
0047 maxItems: 1
0048
0049 ti,camerrx-control:
0050 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0051 items:
0052 - items:
0053 - description: phandle to device control module
0054 - description: offset to the control_camerarx_core register
0055 description:
0056 phandle to the device control module and offset to the
0057 control_camerarx_core register
0058
0059 clocks:
0060 maxItems: 1
0061
0062 clock-names:
0063 const: fck
0064
0065 power-domains:
0066 description:
0067 List of phandle and PM domain specifier as documented in
0068 Documentation/devicetree/bindings/power/power_domain.txt
0069 maxItems: 1
0070
0071 ports:
0072 $ref: /schemas/graph.yaml#/properties/ports
0073
0074 properties:
0075 port@0:
0076 $ref: /schemas/graph.yaml#/$defs/port-base
0077 unevaluatedProperties: false
0078 description: CSI2 Port #0
0079
0080 properties:
0081 endpoint:
0082 $ref: video-interfaces.yaml#
0083 unevaluatedProperties: false
0084
0085 properties:
0086 clock-lanes:
0087 maxItems: 1
0088
0089 data-lanes:
0090 minItems: 1
0091 maxItems: 4
0092
0093 port@1:
0094 $ref: /schemas/graph.yaml#/$defs/port-base
0095 unevaluatedProperties: false
0096 description: CSI2 Port #1
0097
0098 properties:
0099 endpoint:
0100 $ref: video-interfaces.yaml#
0101 unevaluatedProperties: false
0102
0103 properties:
0104 clock-lanes:
0105 maxItems: 1
0106
0107 data-lanes:
0108 minItems: 1
0109 maxItems: 4
0110
0111 required:
0112 - port@0
0113
0114 required:
0115 - compatible
0116 - reg
0117 - reg-names
0118 - interrupts
0119 - ti,camerrx-control
0120
0121 additionalProperties: false
0122
0123 examples:
0124 - |
0125 #include <dt-bindings/interrupt-controller/arm-gic.h>
0126
0127 cal: cal@4845b000 {
0128 compatible = "ti,dra72-cal";
0129 reg = <0x4845B000 0x400>,
0130 <0x4845B800 0x40>,
0131 <0x4845B900 0x40>;
0132 reg-names = "cal_top",
0133 "cal_rx_core0",
0134 "cal_rx_core1";
0135 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0136 ti,camerrx-control = <&scm_conf 0xE94>;
0137
0138 ports {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141
0142 csi2_0: port@0 {
0143 reg = <0>;
0144 csi2_phy0: endpoint {
0145 remote-endpoint = <&csi2_cam0>;
0146 clock-lanes = <0>;
0147 data-lanes = <1 2>;
0148 };
0149 };
0150 };
0151 };
0152
0153 i2c {
0154 clock-frequency = <400000>;
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157
0158 camera-sensor@3c {
0159 compatible = "ovti,ov5640";
0160 reg = <0x3c>;
0161 AVDD-supply = <®_2p8v>;
0162 DOVDD-supply = <®_1p8v>;
0163 DVDD-supply = <®_1p5v>;
0164 clocks = <&clk_ov5640_fixed>;
0165 clock-names = "xclk";
0166
0167 port {
0168 csi2_cam0: endpoint {
0169 remote-endpoint = <&csi2_phy0>;
0170 clock-lanes = <0>;
0171 data-lanes = <1 2>;
0172 };
0173 };
0174 };
0175 };
0176
0177 ...
