0001 STMicroelectronics STi c8sectpfe binding
0002 ============================================
0003
0004 This document describes the c8sectpfe device bindings that is used to get transport
0005 stream data into the SoC on the TS pins, and into DDR for further processing.
0006
0007 It is typically used in conjunction with one or more demodulator and tuner devices
0008 which converts from the RF to digital domain. Demodulators and tuners are usually
0009 located on an external DVB frontend card connected to SoC TS input pins.
0010
0011 Currently 7 TS input (tsin) channels are supported on the stih407 family SoC.
0012
0013 Required properties (controller (parent) node):
0014 - compatible : Should be "stih407-c8sectpfe"
0015
0016 - reg : Address and length of register sets for each device in
0017 "reg-names"
0018
0019 - reg-names : The names of the register addresses corresponding to the
0020 registers filled in "reg":
0021 - c8sectpfe: c8sectpfe registers
0022 - c8sectpfe-ram: c8sectpfe internal sram
0023
0024 - clocks : phandle list of c8sectpfe clocks
0025 - clock-names : should be "c8sectpfe"
0026 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
0027
0028 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
0029 must be defined for each tsin child node.
0030 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration
0031 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
0032
0033
0034 Required properties (tsin (child) node):
0035
0036 - tsin-num : tsin id of the InputBlock (must be between 0 to 6)
0037 - i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected.
0038 - reset-gpios : reset gpio for this tsin channel.
0039
0040 Optional properties (tsin (child) node):
0041
0042 - invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk).
0043 - serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>).
0044 - async-not-sync : Bool property to control if data is received in asynchronous mode
0045 (all bits/bytes with ts_valid or ts_packet asserted are valid).
0046
0047 - dvb-card : Describes the NIM card connected to this tsin channel.
0048
0049 Example:
0050
0051 /* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
0052
0053 c8sectpfe@8a20000 {
0054 compatible = "st,stih407-c8sectpfe";
0055 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
0056 reg-names = "stfe", "stfe-ram";
0057 interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
0058 interrupt-names = "stfe-error-irq", "stfe-idle-irq";
0059 pinctrl-0 = <&pinctrl_tsin0_serial>;
0060 pinctrl-1 = <&pinctrl_tsin0_parallel>;
0061 pinctrl-2 = <&pinctrl_tsin3_serial>;
0062 pinctrl-3 = <&pinctrl_tsin4_serial_alt3>;
0063 pinctrl-4 = <&pinctrl_tsin5_serial_alt1>;
0064 pinctrl-names = "tsin0-serial",
0065 "tsin0-parallel",
0066 "tsin3-serial",
0067 "tsin4-serial",
0068 "tsin5-serial";
0069 clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>;
0070 clock-names = "c8sectpfe";
0071
0072 /* tsin0 is TSA on NIMA */
0073 tsin0: port@0 {
0074 tsin-num = <0>;
0075 serial-not-parallel;
0076 i2c-bus = <&ssc2>;
0077 reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
0078 dvb-card = <STV0367_TDA18212_NIMA_1>;
0079 };
0080
0081 tsin3: port@3 {
0082 tsin-num = <3>;
0083 serial-not-parallel;
0084 i2c-bus = <&ssc3>;
0085 reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>;
0086 dvb-card = <STV0367_TDA18212_NIMB_1>;
0087 };
0088 };
