0001 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SoC Image Signal Processing unit v1
0008
0009 maintainers:
0010 - Helen Koike <helen.koike@collabora.com>
0011
0012 description: |
0013 Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
0014 which contains image processing, scaling, and compression functions.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - rockchip,px30-cif-isp
0020 - rockchip,rk3399-cif-isp
0021
0022 reg:
0023 maxItems: 1
0024
0025 interrupts:
0026 minItems: 1
0027 maxItems: 3
0028
0029 interrupt-names:
0030 items:
0031 - const: isp
0032 - const: mi
0033 - const: mipi
0034
0035 clocks:
0036 minItems: 3
0037 items:
0038 # isp0 and isp1
0039 - description: ISP clock
0040 - description: ISP AXI clock
0041 - description: ISP AHB clock
0042 # only for isp1
0043 - description: ISP Pixel clock
0044
0045 clock-names:
0046 minItems: 3
0047 items:
0048 # isp0 and isp1
0049 - const: isp
0050 - const: aclk
0051 - const: hclk
0052 # only for isp1
0053 - const: pclk
0054
0055 iommus:
0056 maxItems: 1
0057
0058 phys:
0059 maxItems: 1
0060 description: phandle for the PHY port
0061
0062 phy-names:
0063 const: dphy
0064
0065 power-domains:
0066 maxItems: 1
0067
0068 ports:
0069 $ref: /schemas/graph.yaml#/properties/ports
0070
0071 properties:
0072 port@0:
0073 $ref: /schemas/graph.yaml#/$defs/port-base
0074 unevaluatedProperties: false
0075 description: connection point for sensors at MIPI-DPHY RX0
0076
0077 properties:
0078 endpoint:
0079 $ref: video-interfaces.yaml#
0080 unevaluatedProperties: false
0081
0082 properties:
0083 data-lanes:
0084 minItems: 1
0085 maxItems: 4
0086
0087 port@1:
0088 $ref: /schemas/graph.yaml#/$defs/port-base
0089 unevaluatedProperties: false
0090 description: connection point for input on the parallel interface
0091
0092 properties:
0093 bus-type:
0094 enum: [5, 6]
0095
0096 endpoint:
0097 $ref: video-interfaces.yaml#
0098 unevaluatedProperties: false
0099
0100 required:
0101 - bus-type
0102
0103 anyOf:
0104 - required:
0105 - port@0
0106 - required:
0107 - port@1
0108
0109 required:
0110 - compatible
0111 - reg
0112 - interrupts
0113 - clocks
0114 - clock-names
0115 - iommus
0116 - phys
0117 - phy-names
0118 - power-domains
0119 - ports
0120
0121 allOf:
0122 - if:
0123 properties:
0124 compatible:
0125 contains:
0126 const: rockchip,rk3399-cif-isp
0127 then:
0128 properties:
0129 clocks:
0130 minItems: 3
0131 maxItems: 4
0132 clock-names:
0133 minItems: 3
0134 maxItems: 4
0135
0136 - if:
0137 properties:
0138 compatible:
0139 contains:
0140 const: rockchip,px30-cif-isp
0141 then:
0142 required:
0143 - interrupt-names
0144
0145 additionalProperties: false
0146
0147 examples:
0148 - |
0149
0150 #include <dt-bindings/clock/rk3399-cru.h>
0151 #include <dt-bindings/interrupt-controller/arm-gic.h>
0152 #include <dt-bindings/power/rk3399-power.h>
0153
0154 parent0: parent {
0155 #address-cells = <2>;
0156 #size-cells = <2>;
0157
0158 isp0: isp0@ff910000 {
0159 compatible = "rockchip,rk3399-cif-isp";
0160 reg = <0x0 0xff910000 0x0 0x4000>;
0161 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
0162 clocks = <&cru SCLK_ISP0>,
0163 <&cru ACLK_ISP0_WRAPPER>,
0164 <&cru HCLK_ISP0_WRAPPER>;
0165 clock-names = "isp", "aclk", "hclk";
0166 iommus = <&isp0_mmu>;
0167 phys = <&dphy>;
0168 phy-names = "dphy";
0169 power-domains = <&power RK3399_PD_ISP0>;
0170
0171 ports {
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 port@0 {
0176 reg = <0>;
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179
0180 mipi_in_wcam: endpoint@0 {
0181 reg = <0>;
0182 remote-endpoint = <&wcam_out>;
0183 data-lanes = <1 2>;
0184 };
0185
0186 mipi_in_ucam: endpoint@1 {
0187 reg = <1>;
0188 remote-endpoint = <&ucam_out>;
0189 data-lanes = <1>;
0190 };
0191 };
0192 };
0193 };
0194
0195 i2c7: i2c {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198
0199 wcam: camera@36 {
0200 compatible = "ovti,ov5695";
0201 reg = <0x36>;
0202
0203 port {
0204 wcam_out: endpoint {
0205 remote-endpoint = <&mipi_in_wcam>;
0206 data-lanes = <1 2>;
0207 };
0208 };
0209 };
0210
0211 ucam: camera@3c {
0212 compatible = "ovti,ov2685";
0213 reg = <0x3c>;
0214
0215 port {
0216 ucam_out: endpoint {
0217 remote-endpoint = <&mipi_in_ucam>;
0218 data-lanes = <1>;
0219 };
0220 };
0221 };
0222 };
0223 };
0224
0225 - |
0226
0227 #include <dt-bindings/interrupt-controller/arm-gic.h>
0228 #include <dt-bindings/power/px30-power.h>
0229
0230 parent1: parent {
0231 #address-cells = <2>;
0232 #size-cells = <2>;
0233
0234 isp: isp@ff4a0000 {
0235 compatible = "rockchip,px30-cif-isp";
0236 reg = <0x0 0xff4a0000 0x0 0x8000>;
0237 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0238 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0239 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0240 interrupt-names = "isp", "mi", "mipi";
0241 clocks = <&cru SCLK_ISP0>,
0242 <&cru ACLK_ISP0_WRAPPER>,
0243 <&cru HCLK_ISP0_WRAPPER>,
0244 <&cru PCLK_ISP1_WRAPPER>;
0245 clock-names = "isp", "aclk", "hclk", "pclk";
0246 iommus = <&isp_mmu>;
0247 phys = <&csi_dphy>;
0248 phy-names = "dphy";
0249 power-domains = <&power PX30_PD_VI>;
0250
0251 ports {
0252 #address-cells = <1>;
0253 #size-cells = <0>;
0254
0255 port@0 {
0256 reg = <0>;
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259
0260 mipi_in_ucam1: endpoint@0 {
0261 reg = <0>;
0262 remote-endpoint = <&ucam1_out>;
0263 data-lanes = <1 2>;
0264 };
0265 };
0266 };
0267 };
0268
0269 i2c2: i2c {
0270 #address-cells = <1>;
0271 #size-cells = <0>;
0272
0273 ov5695: camera@36 {
0274 compatible = "ovti,ov5647";
0275 reg = <0x36>;
0276 clocks = <&cru SCLK_CIF_OUT>;
0277
0278 port {
0279 ucam1_out: endpoint {
0280 remote-endpoint = <&mipi_in_ucam1>;
0281 data-lanes = <1 2>;
0282 };
0283 };
0284 };
0285 };
0286 };
