0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Hantro G1 VPU encoders implemented on Rockchip SoCs
0009
0010 maintainers:
0011 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
0012
0013 description:
0014 Hantro G1 video encode-only accelerators present on Rockchip SoCs.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - rockchip,rk3568-vepu
0020
0021 reg:
0022 maxItems: 1
0023
0024 interrupts:
0025 maxItems: 1
0026
0027 clocks:
0028 maxItems: 2
0029
0030 clock-names:
0031 items:
0032 - const: aclk
0033 - const: hclk
0034
0035 power-domains:
0036 maxItems: 1
0037
0038 iommus:
0039 maxItems: 1
0040
0041 required:
0042 - compatible
0043 - reg
0044 - interrupts
0045 - clocks
0046 - clock-names
0047
0048 additionalProperties: false
0049
0050 examples:
0051 - |
0052 #include <dt-bindings/clock/rk3568-cru.h>
0053 #include <dt-bindings/interrupt-controller/arm-gic.h>
0054 #include <dt-bindings/power/rk3568-power.h>
0055
0056 bus {
0057 #address-cells = <2>;
0058 #size-cells = <2>;
0059
0060 vepu: video-codec@fdee0000 {
0061 compatible = "rockchip,rk3568-vepu";
0062 reg = <0x0 0xfdee0000 0x0 0x800>;
0063 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0064 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
0065 clock-names = "aclk", "hclk";
0066 iommus = <&vepu_mmu>;
0067 power-domains = <&power RK3568_PD_RGA>;
0068 };
0069 };
