0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/renesas,fdp1.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas R-Car Fine Display Processor (FDP1)
0008
0009 maintainers:
0010 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0011
0012 description:
0013 The FDP1 is a de-interlacing module which converts interlaced video to
0014 progressive video. It is capable of performing pixel format conversion
0015 between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are
0016 supported as an input to the module.
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - renesas,fdp1
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 maxItems: 1
0031
0032 power-domains:
0033 maxItems: 1
0034
0035 resets:
0036 maxItems: 1
0037
0038 renesas,fcp:
0039 $ref: /schemas/types.yaml#/definitions/phandle
0040 description:
0041 A phandle referencing the FCP that handles memory accesses for the FDP1.
0042 Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
0043
0044 required:
0045 - compatible
0046 - reg
0047 - interrupts
0048 - clocks
0049 - power-domains
0050 - resets
0051
0052 additionalProperties: false
0053
0054 examples:
0055 - |
0056 #include <dt-bindings/clock/renesas-cpg-mssr.h>
0057 #include <dt-bindings/interrupt-controller/arm-gic.h>
0058 #include <dt-bindings/power/r8a7795-sysc.h>
0059
0060 fdp1@fe940000 {
0061 compatible = "renesas,fdp1";
0062 reg = <0xfe940000 0x2400>;
0063 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
0064 clocks = <&cpg CPG_MOD 119>;
0065 power-domains = <&sysc R8A7795_PD_A3VP>;
0066 resets = <&cpg 119>;
0067 renesas,fcp = <&fcpf0>;
0068 };
0069 ...
