0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
0008
0009 maintainers:
0010 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
0011 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
0012
0013 description: |
0014 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
0015 representation of DRIF interfacing with a master device is shown below.
0016
0017 +---------------------+ +---------------------+
0018 | |-----SCK------->|CLK |
0019 | Master |-----SS-------->|SYNC DRIFn (slave) |
0020 | |-----SD0------->|D0 |
0021 | |-----SD1------->|D1 |
0022 +---------------------+ +---------------------+
0023
0024 As per datasheet, each DRIF channel (drifn) is made up of two internal
0025 channels (drifn0 & drifn1). These two internal channels share the common
0026 CLK & SYNC. Each internal channel has its own dedicated resources like
0027 irq, dma channels, address space & clock. This internal split is not
0028 visible to the external master device.
0029
0030 The device tree model represents each internal channel as a separate node.
0031 The internal channels sharing the CLK & SYNC are tied together by their
0032 phandles using a property called "renesas,bonding". For the rest of
0033 the documentation, unless explicitly stated, the word channel implies an
0034 internal channel.
0035
0036 When both internal channels are enabled they need to be managed together
0037 as one (i.e.) they cannot operate alone as independent devices. Out of the
0038 two, one of them needs to act as a primary device that accepts common
0039 properties of both the internal channels. This channel is identified by a
0040 property called "renesas,primary-bond".
0041
0042 To summarize,
0043 * When both the internal channels that are bonded together are enabled,
0044 the zeroth channel is selected as primary-bond. This channels accepts
0045 properties common to all the members of the bond.
0046 * When only one of the bonded channels need to be enabled, the property
0047 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
0048 enabled channel can act alone as any other independent device.
0049
0050 properties:
0051 compatible:
0052 items:
0053 - enum:
0054 - renesas,r8a7795-drif # R-Car H3
0055 - renesas,r8a7796-drif # R-Car M3-W
0056 - renesas,r8a77965-drif # R-Car M3-N
0057 - renesas,r8a77990-drif # R-Car E3
0058 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
0059
0060 reg:
0061 maxItems: 1
0062
0063 interrupts:
0064 maxItems: 1
0065
0066 clocks:
0067 maxItems: 1
0068
0069 clock-names:
0070 const: fck
0071
0072 resets:
0073 maxItems: 1
0074
0075 dmas:
0076 minItems: 1
0077 maxItems: 2
0078
0079 dma-names:
0080 minItems: 1
0081 items:
0082 - const: rx
0083 - const: rx
0084
0085 renesas,bonding:
0086 $ref: /schemas/types.yaml#/definitions/phandle
0087 description:
0088 The phandle to the other internal channel of DRIF
0089
0090 power-domains:
0091 maxItems: 1
0092
0093 renesas,primary-bond:
0094 type: boolean
0095 description:
0096 Indicates that the channel acts as primary among the bonded channels.
0097
0098 port:
0099 $ref: /schemas/graph.yaml#/$defs/port-base
0100 unevaluatedProperties: false
0101 description:
0102 Child port node corresponding to the data input. The port node must
0103 contain at least one endpoint.
0104
0105 properties:
0106 endpoint:
0107 $ref: /schemas/graph.yaml#/$defs/endpoint-base
0108 unevaluatedProperties: false
0109
0110 properties:
0111 sync-active:
0112 $ref: /schemas/types.yaml#/definitions/uint32
0113 enum: [0, 1]
0114 description:
0115 Indicates sync signal polarity, 0/1 for low/high respectively.
0116 This property maps to SYNCAC bit in the hardware manual. The
0117 default is 1 (active high).
0118
0119 required:
0120 - compatible
0121 - reg
0122 - interrupts
0123 - clocks
0124 - clock-names
0125 - resets
0126 - dmas
0127 - dma-names
0128 - renesas,bonding
0129 - power-domains
0130
0131 allOf:
0132 - if:
0133 required:
0134 - renesas,primary-bond
0135 then:
0136 required:
0137 - pinctrl-0
0138 - pinctrl-names
0139 - port
0140
0141 - if:
0142 required:
0143 - port
0144 then:
0145 required:
0146 - pinctrl-0
0147 - pinctrl-names
0148 else:
0149 properties:
0150 pinctrl-0: false
0151 pinctrl-names: false
0152
0153 additionalProperties: false
0154
0155 examples:
0156 # Example with both internal channels enabled.
0157 #
0158 # When interfacing with a third party tuner device with two data pins as shown
0159 # below.
0160 #
0161 # +---------------------+ +---------------------+
0162 # | |-----SCK------->|CLK |
0163 # | Master |-----SS-------->|SYNC DRIFn (slave) |
0164 # | |-----SD0------->|D0 |
0165 # | |-----SD1------->|D1 |
0166 # +---------------------+ +---------------------+
0167 - |
0168 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
0169 #include <dt-bindings/interrupt-controller/arm-gic.h>
0170 #include <dt-bindings/power/r8a7795-sysc.h>
0171
0172 soc {
0173 #address-cells = <2>;
0174 #size-cells = <2>;
0175
0176 drif00: rif@e6f40000 {
0177 compatible = "renesas,r8a7795-drif",
0178 "renesas,rcar-gen3-drif";
0179 reg = <0 0xe6f40000 0 0x64>;
0180 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0181 clocks = <&cpg CPG_MOD 515>;
0182 clock-names = "fck";
0183 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
0184 dma-names = "rx", "rx";
0185 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
0186 renesas,bonding = <&drif01>;
0187 resets = <&cpg 515>;
0188 renesas,primary-bond;
0189 pinctrl-0 = <&drif0_pins>;
0190 pinctrl-names = "default";
0191 port {
0192 drif0_ep: endpoint {
0193 remote-endpoint = <&tuner_ep>;
0194 };
0195 };
0196 };
0197
0198 drif01: rif@e6f50000 {
0199 compatible = "renesas,r8a7795-drif",
0200 "renesas,rcar-gen3-drif";
0201 reg = <0 0xe6f50000 0 0x64>;
0202 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0203 clocks = <&cpg CPG_MOD 514>;
0204 clock-names = "fck";
0205 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
0206 dma-names = "rx", "rx";
0207 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
0208 renesas,bonding = <&drif00>;
0209 resets = <&cpg 514>;
0210 };
0211 };
0212
0213 # Example with internal channel 1 alone enabled.
0214 #
0215 # When interfacing with a third party tuner device with one data pin as shown
0216 # below.
0217 #
0218 # +---------------------+ +---------------------+
0219 # | |-----SCK------->|CLK |
0220 # | Master |-----SS-------->|SYNC DRIFn (slave) |
0221 # | | |D0 (unused) |
0222 # | |-----SD-------->|D1 |
0223 # +---------------------+ +---------------------+
0224 - |
0225 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
0226 #include <dt-bindings/interrupt-controller/arm-gic.h>
0227 #include <dt-bindings/power/r8a7795-sysc.h>
0228
0229 soc {
0230 #address-cells = <2>;
0231 #size-cells = <2>;
0232
0233 drif10: rif@e6f60000 {
0234 compatible = "renesas,r8a7795-drif",
0235 "renesas,rcar-gen3-drif";
0236 reg = <0 0xe6f60000 0 0x64>;
0237 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0238 clocks = <&cpg CPG_MOD 513>;
0239 clock-names = "fck";
0240 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
0241 dma-names = "rx", "rx";
0242 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
0243 resets = <&cpg 513>;
0244 renesas,bonding = <&drif11>;
0245 };
0246
0247 drif11: rif@e6f70000 {
0248 compatible = "renesas,r8a7795-drif",
0249 "renesas,rcar-gen3-drif";
0250 reg = <0 0xe6f70000 0 0x64>;
0251 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0252 clocks = <&cpg CPG_MOD 512>;
0253 clock-names = "fck";
0254 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
0255 dma-names = "rx", "rx";
0256 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
0257 resets = <&cpg 512>;
0258 renesas,bonding = <&drif10>;
0259 pinctrl-0 = <&drif1_pins>;
0260 pinctrl-names = "default";
0261 port {
0262 drif1_ep: endpoint {
0263 remote-endpoint = <&tuner_ep1>;
0264 sync-active = <0>;
0265 };
0266 };
0267 };
0268 };
0269 ...
