0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Qualcomm CAMSS ISP
0009
0010 maintainers:
0011 - Robert Foss <robert.foss@linaro.org>
0012
0013 description: |
0014 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
0015
0016 properties:
0017 compatible:
0018 const: qcom,sdm845-camss
0019
0020 clocks:
0021 minItems: 36
0022 maxItems: 36
0023
0024 clock-names:
0025 items:
0026 - const: camnoc_axi
0027 - const: cpas_ahb
0028 - const: cphy_rx_src
0029 - const: csi0
0030 - const: csi0_src
0031 - const: csi1
0032 - const: csi1_src
0033 - const: csi2
0034 - const: csi2_src
0035 - const: csiphy0
0036 - const: csiphy0_timer
0037 - const: csiphy0_timer_src
0038 - const: csiphy1
0039 - const: csiphy1_timer
0040 - const: csiphy1_timer_src
0041 - const: csiphy2
0042 - const: csiphy2_timer
0043 - const: csiphy2_timer_src
0044 - const: csiphy3
0045 - const: csiphy3_timer
0046 - const: csiphy3_timer_src
0047 - const: gcc_camera_ahb
0048 - const: gcc_camera_axi
0049 - const: slow_ahb_src
0050 - const: soc_ahb
0051 - const: vfe0_axi
0052 - const: vfe0
0053 - const: vfe0_cphy_rx
0054 - const: vfe0_src
0055 - const: vfe1_axi
0056 - const: vfe1
0057 - const: vfe1_cphy_rx
0058 - const: vfe1_src
0059 - const: vfe_lite
0060 - const: vfe_lite_cphy_rx
0061 - const: vfe_lite_src
0062
0063 interrupts:
0064 minItems: 10
0065 maxItems: 10
0066
0067 interrupt-names:
0068 items:
0069 - const: csid0
0070 - const: csid1
0071 - const: csid2
0072 - const: csiphy0
0073 - const: csiphy1
0074 - const: csiphy2
0075 - const: csiphy3
0076 - const: vfe0
0077 - const: vfe1
0078 - const: vfe_lite
0079
0080 iommus:
0081 maxItems: 4
0082
0083 power-domains:
0084 items:
0085 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
0086 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
0087 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
0088
0089 ports:
0090 $ref: /schemas/graph.yaml#/properties/ports
0091
0092 description:
0093 CSI input ports.
0094
0095 properties:
0096 port@0:
0097 $ref: /schemas/graph.yaml#/$defs/port-base
0098 unevaluatedProperties: false
0099 description:
0100 Input port for receiving CSI data.
0101
0102 properties:
0103 endpoint:
0104 $ref: video-interfaces.yaml#
0105 unevaluatedProperties: false
0106
0107 properties:
0108 data-lanes:
0109 minItems: 1
0110 maxItems: 4
0111
0112 required:
0113 - data-lanes
0114
0115 port@1:
0116 $ref: /schemas/graph.yaml#/$defs/port-base
0117 unevaluatedProperties: false
0118 description:
0119 Input port for receiving CSI data.
0120
0121 properties:
0122 endpoint:
0123 $ref: video-interfaces.yaml#
0124 unevaluatedProperties: false
0125
0126 properties:
0127 data-lanes:
0128 minItems: 1
0129 maxItems: 4
0130
0131 required:
0132 - data-lanes
0133
0134 port@2:
0135 $ref: /schemas/graph.yaml#/$defs/port-base
0136 unevaluatedProperties: false
0137 description:
0138 Input port for receiving CSI data.
0139
0140 properties:
0141 endpoint:
0142 $ref: video-interfaces.yaml#
0143 unevaluatedProperties: false
0144
0145 properties:
0146 data-lanes:
0147 minItems: 1
0148 maxItems: 4
0149
0150 required:
0151 - data-lanes
0152
0153 port@3:
0154 $ref: /schemas/graph.yaml#/$defs/port-base
0155 unevaluatedProperties: false
0156 description:
0157 Input port for receiving CSI data.
0158
0159 properties:
0160 endpoint:
0161 $ref: video-interfaces.yaml#
0162 unevaluatedProperties: false
0163
0164 properties:
0165 data-lanes:
0166 minItems: 1
0167 maxItems: 4
0168
0169 required:
0170 - data-lanes
0171
0172 reg:
0173 minItems: 10
0174 maxItems: 10
0175
0176 reg-names:
0177 items:
0178 - const: csid0
0179 - const: csid1
0180 - const: csid2
0181 - const: csiphy0
0182 - const: csiphy1
0183 - const: csiphy2
0184 - const: csiphy3
0185 - const: vfe0
0186 - const: vfe1
0187 - const: vfe_lite
0188
0189 vdda-phy-supply:
0190 description:
0191 Phandle to a regulator supply to PHY core block.
0192
0193 vdda-pll-supply:
0194 description:
0195 Phandle to 1.8V regulator supply to PHY refclk pll block.
0196
0197 required:
0198 - clock-names
0199 - clocks
0200 - compatible
0201 - interrupt-names
0202 - interrupts
0203 - iommus
0204 - power-domains
0205 - reg
0206 - reg-names
0207 - vdda-phy-supply
0208 - vdda-pll-supply
0209
0210 additionalProperties: false
0211
0212 examples:
0213 - |
0214 #include <dt-bindings/interrupt-controller/arm-gic.h>
0215 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
0216 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0217
0218 soc {
0219 #address-cells = <2>;
0220 #size-cells = <2>;
0221
0222 camss: camss@a00000 {
0223 compatible = "qcom,sdm845-camss";
0224
0225 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
0226 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
0227 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
0228 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
0229 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
0230 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
0231 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
0232 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
0233 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
0234 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
0235 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
0236 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
0237 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
0238 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
0239 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
0240 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
0241 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
0242 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
0243 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
0244 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
0245 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
0246 <&gcc GCC_CAMERA_AHB_CLK>,
0247 <&gcc GCC_CAMERA_AXI_CLK>,
0248 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
0249 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
0250 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
0251 <&clock_camcc CAM_CC_IFE_0_CLK>,
0252 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
0253 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
0254 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
0255 <&clock_camcc CAM_CC_IFE_1_CLK>,
0256 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
0257 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
0258 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
0259 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
0260 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
0261
0262 clock-names = "camnoc_axi",
0263 "cpas_ahb",
0264 "cphy_rx_src",
0265 "csi0",
0266 "csi0_src",
0267 "csi1",
0268 "csi1_src",
0269 "csi2",
0270 "csi2_src",
0271 "csiphy0",
0272 "csiphy0_timer",
0273 "csiphy0_timer_src",
0274 "csiphy1",
0275 "csiphy1_timer",
0276 "csiphy1_timer_src",
0277 "csiphy2",
0278 "csiphy2_timer",
0279 "csiphy2_timer_src",
0280 "csiphy3",
0281 "csiphy3_timer",
0282 "csiphy3_timer_src",
0283 "gcc_camera_ahb",
0284 "gcc_camera_axi",
0285 "slow_ahb_src",
0286 "soc_ahb",
0287 "vfe0_axi",
0288 "vfe0",
0289 "vfe0_cphy_rx",
0290 "vfe0_src",
0291 "vfe1_axi",
0292 "vfe1",
0293 "vfe1_cphy_rx",
0294 "vfe1_src",
0295 "vfe_lite",
0296 "vfe_lite_cphy_rx",
0297 "vfe_lite_src";
0298
0299 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
0305 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
0306 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
0307 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
0309
0310 interrupt-names = "csid0",
0311 "csid1",
0312 "csid2",
0313 "csiphy0",
0314 "csiphy1",
0315 "csiphy2",
0316 "csiphy3",
0317 "vfe0",
0318 "vfe1",
0319 "vfe_lite";
0320
0321 iommus = <&apps_smmu 0x0808 0x0>,
0322 <&apps_smmu 0x0810 0x8>,
0323 <&apps_smmu 0x0c08 0x0>,
0324 <&apps_smmu 0x0c10 0x8>;
0325
0326 power-domains = <&clock_camcc IFE_0_GDSC>,
0327 <&clock_camcc IFE_1_GDSC>,
0328 <&clock_camcc TITAN_TOP_GDSC>;
0329
0330 reg = <0 0xacb3000 0 0x1000>,
0331 <0 0xacba000 0 0x1000>,
0332 <0 0xacc8000 0 0x1000>,
0333 <0 0xac65000 0 0x1000>,
0334 <0 0xac66000 0 0x1000>,
0335 <0 0xac67000 0 0x1000>,
0336 <0 0xac68000 0 0x1000>,
0337 <0 0xacaf000 0 0x4000>,
0338 <0 0xacb6000 0 0x4000>,
0339 <0 0xacc4000 0 0x4000>;
0340
0341 reg-names = "csid0",
0342 "csid1",
0343 "csid2",
0344 "csiphy0",
0345 "csiphy1",
0346 "csiphy2",
0347 "csiphy3",
0348 "vfe0",
0349 "vfe1",
0350 "vfe_lite";
0351
0352 vdda-phy-supply = <&vreg_l1a_0p875>;
0353 vdda-pll-supply = <&vreg_l26a_1p2>;
0354
0355 ports {
0356 #address-cells = <1>;
0357 #size-cells = <0>;
0358 };
0359 };
0360 };
