0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8MQ MIPI CSI-2 receiver
0008
0009 maintainers:
0010 - Martin Kepplinger <martin.kepplinger@puri.sm>
0011
0012 description: |-
0013 This binding covers the CSI-2 RX PHY and host controller included in the
0014 NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
0015 input imaging devices.
0016
0017 properties:
0018 compatible:
0019 enum:
0020 - fsl,imx8mq-mipi-csi2
0021
0022 reg:
0023 maxItems: 1
0024
0025 clocks:
0026 items:
0027 - description: core is the RX Controller Core Clock input. This clock
0028 must be exactly equal to or faster than the receive
0029 byteclock from the RX DPHY.
0030 - description: esc is the Rx Escape Clock. This must be the same escape
0031 clock that the RX DPHY receives.
0032 - description: ui is the pixel clock (phy_ref up to 333Mhz).
0033 See the reference manual for details.
0034
0035 clock-names:
0036 items:
0037 - const: core
0038 - const: esc
0039 - const: ui
0040
0041 power-domains:
0042 maxItems: 1
0043
0044 resets:
0045 items:
0046 - description: CORE_RESET reset register bit definition
0047 - description: PHY_REF_RESET reset register bit definition
0048 - description: ESC_RESET reset register bit definition
0049
0050 fsl,mipi-phy-gpr:
0051 description: |
0052 The phandle to the imx8mq syscon iomux-gpr with the register
0053 for setting RX_ENABLE for the mipi receiver.
0054
0055 The format should be as follows:
0056 <gpr req_gpr>
0057 gpr is the phandle to general purpose register node.
0058 req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
0059 $ref: /schemas/types.yaml#/definitions/phandle-array
0060 items:
0061 - items:
0062 - description: The 'gpr' is the phandle to general purpose register node.
0063 - description: The 'req_gpr' is the gpr register offset containing
0064 CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
0065 maximum: 0xff
0066
0067 interconnects:
0068 maxItems: 1
0069
0070 interconnect-names:
0071 const: dram
0072
0073 ports:
0074 $ref: /schemas/graph.yaml#/properties/ports
0075
0076 properties:
0077 port@0:
0078 $ref: /schemas/graph.yaml#/$defs/port-base
0079 unevaluatedProperties: false
0080 description:
0081 Input port node, single endpoint describing the CSI-2 transmitter.
0082
0083 properties:
0084 endpoint:
0085 $ref: video-interfaces.yaml#
0086 unevaluatedProperties: false
0087
0088 properties:
0089 data-lanes:
0090 minItems: 1
0091 items:
0092 - const: 1
0093 - const: 2
0094 - const: 3
0095 - const: 4
0096
0097 required:
0098 - data-lanes
0099
0100 port@1:
0101 $ref: /schemas/graph.yaml#/properties/port
0102 description:
0103 Output port node
0104
0105 required:
0106 - port@0
0107 - port@1
0108
0109 required:
0110 - compatible
0111 - reg
0112 - clocks
0113 - clock-names
0114 - power-domains
0115 - resets
0116 - fsl,mipi-phy-gpr
0117 - ports
0118
0119 additionalProperties: false
0120
0121 examples:
0122 - |
0123 #include <dt-bindings/clock/imx8mq-clock.h>
0124 #include <dt-bindings/interconnect/imx8mq.h>
0125 #include <dt-bindings/reset/imx8mq-reset.h>
0126
0127 csi@30a70000 {
0128 compatible = "fsl,imx8mq-mipi-csi2";
0129 reg = <0x30a70000 0x1000>;
0130 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
0131 <&clk IMX8MQ_CLK_CSI1_ESC>,
0132 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
0133 clock-names = "core", "esc", "ui";
0134 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
0135 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
0136 <&clk IMX8MQ_CLK_CSI1_ESC>;
0137 assigned-clock-rates = <266000000>, <200000000>, <66000000>;
0138 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
0139 <&clk IMX8MQ_SYS2_PLL_1000M>,
0140 <&clk IMX8MQ_SYS1_PLL_800M>;
0141 power-domains = <&pgc_mipi_csi1>;
0142 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
0143 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
0144 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
0145 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
0146 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
0147 interconnect-names = "dram";
0148
0149 ports {
0150 #address-cells = <1>;
0151 #size-cells = <0>;
0152
0153 port@0 {
0154 reg = <0>;
0155
0156 imx8mm_mipi_csi_in: endpoint {
0157 remote-endpoint = <&imx477_out>;
0158 data-lanes = <1 2 3 4>;
0159 };
0160 };
0161
0162 port@1 {
0163 reg = <1>;
0164
0165 imx8mm_mipi_csi_out: endpoint {
0166 remote-endpoint = <&csi_in>;
0167 };
0168 };
0169 };
0170 };
0171
0172 ...
