0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
0008
0009 maintainers:
0010 - Rui Miguel Silva <rmfrfs@gmail.com>
0011 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0012
0013 description: |-
0014 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
0015 receiver IP core named CSIS. The IP core originates from Samsung, and may be
0016 compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
0017 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
0018
0019 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
0020 completely wrapped by the CSIS and doesn't expose a control interface of its
0021 own. This binding thus covers both IP cores.
0022
0023 properties:
0024 compatible:
0025 oneOf:
0026 - enum:
0027 - fsl,imx7-mipi-csi2
0028 - fsl,imx8mm-mipi-csi2
0029 - items:
0030 - enum:
0031 - fsl,imx8mp-mipi-csi2
0032 - const: fsl,imx8mm-mipi-csi2
0033
0034 reg:
0035 maxItems: 1
0036
0037 interrupts:
0038 maxItems: 1
0039
0040 clocks:
0041 minItems: 3
0042 items:
0043 - description: The peripheral clock (a.k.a. APB clock)
0044 - description: The external clock (optionally used as the pixel clock)
0045 - description: The MIPI D-PHY clock
0046 - description: The AXI clock
0047
0048 clock-names:
0049 minItems: 3
0050 items:
0051 - const: pclk
0052 - const: wrap
0053 - const: phy
0054 - const: axi
0055
0056 power-domains:
0057 maxItems: 1
0058
0059 phy-supply:
0060 description: The MIPI D-PHY digital power supply
0061
0062 resets:
0063 items:
0064 - description: MIPI D-PHY slave reset
0065
0066 clock-frequency:
0067 description: The desired external clock ("wrap") frequency, in Hz
0068 default: 166000000
0069
0070 ports:
0071 $ref: /schemas/graph.yaml#/properties/ports
0072
0073 properties:
0074 port@0:
0075 $ref: /schemas/graph.yaml#/$defs/port-base
0076 unevaluatedProperties: false
0077 description:
0078 Input port node, single endpoint describing the CSI-2 transmitter.
0079
0080 properties:
0081 endpoint:
0082 $ref: video-interfaces.yaml#
0083 unevaluatedProperties: false
0084
0085 properties:
0086 data-lanes:
0087 description:
0088 Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
0089 minItems: 1
0090 items:
0091 - const: 1
0092 - const: 2
0093 - const: 3
0094 - const: 4
0095
0096 required:
0097 - data-lanes
0098
0099 port@1:
0100 $ref: /schemas/graph.yaml#/properties/port
0101 description:
0102 Output port node
0103
0104 required:
0105 - compatible
0106 - reg
0107 - interrupts
0108 - clocks
0109 - clock-names
0110 - power-domains
0111 - ports
0112
0113 additionalProperties: false
0114
0115 allOf:
0116 - if:
0117 properties:
0118 compatible:
0119 contains:
0120 const: fsl,imx7-mipi-csi2
0121 then:
0122 required:
0123 - phy-supply
0124 - resets
0125 else:
0126 properties:
0127 clocks:
0128 minItems: 4
0129 clock-names:
0130 minItems: 4
0131 phy-supply: false
0132 resets: false
0133
0134 examples:
0135 - |
0136 #include <dt-bindings/clock/imx7d-clock.h>
0137 #include <dt-bindings/interrupt-controller/arm-gic.h>
0138 #include <dt-bindings/interrupt-controller/irq.h>
0139 #include <dt-bindings/reset/imx7-reset.h>
0140
0141 mipi-csi@30750000 {
0142 compatible = "fsl,imx7-mipi-csi2";
0143 reg = <0x30750000 0x10000>;
0144 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0145
0146 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
0147 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
0148 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
0149 clock-names = "pclk", "wrap", "phy";
0150 clock-frequency = <166000000>;
0151
0152 power-domains = <&pgc_mipi_phy>;
0153 phy-supply = <®_1p0d>;
0154 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
0155
0156 ports {
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159
0160 port@0 {
0161 reg = <0>;
0162
0163 mipi_from_sensor: endpoint {
0164 remote-endpoint = <&ov2680_to_mipi>;
0165 data-lanes = <1>;
0166 };
0167 };
0168
0169 port@1 {
0170 reg = <1>;
0171
0172 mipi_vc0_to_csi_mux: endpoint {
0173 remote-endpoint = <&csi_mux_from_mipi_vc0>;
0174 };
0175 };
0176 };
0177 };
0178
0179 - |
0180 #include <dt-bindings/clock/imx8mm-clock.h>
0181 #include <dt-bindings/interrupt-controller/arm-gic.h>
0182 #include <dt-bindings/interrupt-controller/irq.h>
0183
0184 mipi-csi@32e30000 {
0185 compatible = "fsl,imx8mm-mipi-csi2";
0186 reg = <0x32e30000 0x1000>;
0187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0188 clock-frequency = <333000000>;
0189 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
0190 <&clk IMX8MM_CLK_CSI1_ROOT>,
0191 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
0192 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
0193 clock-names = "pclk", "wrap", "phy", "axi";
0194 power-domains = <&mipi_pd>;
0195
0196 ports {
0197 #address-cells = <1>;
0198 #size-cells = <0>;
0199
0200 port@0 {
0201 reg = <0>;
0202
0203 imx8mm_mipi_csi_in: endpoint {
0204 remote-endpoint = <&imx477_out>;
0205 data-lanes = <1 2 3 4>;
0206 };
0207 };
0208
0209 port@1 {
0210 reg = <1>;
0211
0212 imx8mm_mipi_csi_out: endpoint {
0213 remote-endpoint = <&csi_in>;
0214 };
0215 };
0216 };
0217 };
0218
0219 ...
