0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Video Decoder Engine
0008
0009 maintainers:
0010 - Dmitry Osipenko <digetx@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Thierry Reding <thierry.reding@gmail.com>
0013
0014 properties:
0015 compatible:
0016 oneOf:
0017 - items:
0018 - enum:
0019 - nvidia,tegra132-vde
0020 - nvidia,tegra124-vde
0021 - nvidia,tegra114-vde
0022 - items:
0023 - const: nvidia,tegra30-vde
0024 - const: nvidia,tegra20-vde
0025 - items:
0026 - const: nvidia,tegra20-vde
0027
0028 reg:
0029 maxItems: 9
0030
0031 reg-names:
0032 items:
0033 - const: sxe
0034 - const: bsev
0035 - const: mbe
0036 - const: ppe
0037 - const: mce
0038 - const: tfe
0039 - const: ppb
0040 - const: vdma
0041 - const: frameid
0042
0043 clocks:
0044 maxItems: 1
0045
0046 resets:
0047 maxItems: 2
0048
0049 reset-names:
0050 items:
0051 - const: vde
0052 - const: mc
0053
0054 interrupts:
0055 maxItems: 3
0056
0057 interrupt-names:
0058 items:
0059 - const: sync-token
0060 - const: bsev
0061 - const: sxe
0062
0063 iommus:
0064 maxItems: 1
0065
0066 iram:
0067 $ref: /schemas/types.yaml#/definitions/phandle
0068 description:
0069 Phandle of the SRAM MMIO node.
0070
0071 operating-points-v2:
0072 description:
0073 Should contain freqs and voltages and opp-supported-hw property,
0074 which is a bitfield indicating SoC speedo or process ID mask.
0075
0076 power-domains:
0077 maxItems: 1
0078 description:
0079 Phandle to the SoC core power domain.
0080
0081 required:
0082 - compatible
0083 - reg
0084 - reg-names
0085 - clocks
0086 - resets
0087 - reset-names
0088 - interrupts
0089 - interrupt-names
0090
0091 additionalProperties: false
0092
0093 examples:
0094 - |
0095 video-codec@6001a000 {
0096 compatible = "nvidia,tegra20-vde";
0097 reg = <0x6001a000 0x1000>, /* Syntax Engine */
0098 <0x6001b000 0x1000>, /* Video Bitstream Engine */
0099 <0x6001c000 0x100>, /* Macroblock Engine */
0100 <0x6001c200 0x100>, /* Post-processing Engine */
0101 <0x6001c400 0x100>, /* Motion Compensation Engine */
0102 <0x6001c600 0x100>, /* Transform Engine */
0103 <0x6001c800 0x100>, /* Pixel prediction block */
0104 <0x6001ca00 0x100>, /* Video DMA */
0105 <0x6001d800 0x300>; /* Video frame controls */
0106 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
0107 "tfe", "ppb", "vdma", "frameid";
0108 iram = <&iram>; /* IRAM MMIO region */
0109 interrupts = <0 9 4>, /* Sync token */
0110 <0 10 4>, /* BSE-V */
0111 <0 12 4>; /* SXE */
0112 interrupt-names = "sync-token", "bsev", "sxe";
0113 clocks = <&clk 61>;
0114 reset-names = "vde", "mc";
0115 resets = <&rst 61>, <&mem 13>;
0116 iommus = <&mem 15>;
0117 operating-points-v2 = <&dvfs_opp_table>;
0118 power-domains = <&domain>;
0119 };
