bindings/media/microchip%2Cxisc.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2021 Microchip Technology, Inc.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/media/microchip,xisc.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Microchip eXtended Image Sensor Controller (XISC)
0009
0010 maintainers:
0011   - Eugen Hristev <eugen.hristev@microchip.com>
0012
0013 description: |
0014   The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
0015   Microchip AT91 SAM family of devices.
0016
0017   The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
0018   The source can be either a demuxer from a CSI2 type of bus, or a simple direct bridge to a
0019   parallel sensor.
0020
0021   The XISC provides one clock output that is used to clock the demuxer/bridge.
0022
0023 properties:
0024   compatible:
0025     const: microchip,sama7g5-isc
0026
0027   reg:
0028     maxItems: 1
0029
0030   interrupts:
0031     maxItems: 1
0032
0033   clocks:
0034     maxItems: 1
0035
0036   clock-names:
0037     items:
0038       - const: hclock
0039
0040   '#clock-cells':
0041     const: 0
0042
0043   clock-output-names:
0044     const: isc-mck
0045
0046   microchip,mipi-mode:
0047     type: boolean
0048     description:
0049       As the XISC is usually connected to a demux/bridge, the XISC receives
0050       the same type of input, however, it should be aware of the type of
0051       signals received. The mipi-mode enables different internal handling
0052       of the data and clock lines.
0053
0054   port:
0055     $ref: /schemas/graph.yaml#/$defs/port-base
0056     description:
0057       Input port node, single endpoint describing the input pad.
0058
0059     properties:
0060       endpoint:
0061         $ref: video-interfaces.yaml#
0062
0063         properties:
0064           bus-type:
0065             enum: [5, 6]
0066
0067           remote-endpoint: true
0068
0069           bus-width:
0070             enum: [8, 9, 10, 11, 12, 14]
0071             default: 12
0072
0073           hsync-active:
0074             enum: [0, 1]
0075             default: 1
0076
0077           vsync-active:
0078             enum: [0, 1]
0079             default: 1
0080
0081           pclk-sample:
0082             enum: [0, 1]
0083             default: 1
0084
0085         required:
0086           - remote-endpoint
0087           - bus-type
0088
0089         additionalProperties: false
0090
0091     additionalProperties: false
0092
0093 required:
0094   - compatible
0095   - reg
0096   - clocks
0097   - clock-names
0098   - '#clock-cells'
0099   - clock-output-names
0100   - port
0101
0102 additionalProperties: false
0103
0104 examples:
0105   - |
0106     #include <dt-bindings/interrupt-controller/arm-gic.h>
0107     #include <dt-bindings/clock/at91.h>
0108     #include <dt-bindings/interrupt-controller/irq.h>
0109
0110     xisc: xisc@e1408000 {
0111         compatible = "microchip,sama7g5-isc";
0112         reg = <0xe1408000 0x2000>;
0113         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0114         clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
0115         clock-names = "hclock";
0116         #clock-cells = <0>;
0117         clock-output-names = "isc-mck";
0118
0119         port {
0120                 xisc_in: endpoint {
0121                        bus-type = <5>; /* Parallel */
0122                        remote-endpoint = <&csi2dc_out>;
0123                        hsync-active = <1>;
0124                        vsync-active = <1>;
0125                        bus-width = <12>;
0126                 };
0127         };
0128     };