0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip CSI2 Demux Controller (CSI2DC)
0008
0009 maintainers:
0010 - Eugen Hristev <eugen.hristev@microchip.com>
0011
0012 description:
0013 CSI2DC - Camera Serial Interface 2 Demux Controller
0014
0015 CSI2DC is a hardware block that receives incoming data from either from an
0016 IDI interface or from a parallel bus interface.
0017 It filters IDI packets based on their data type and virtual channel
0018 identifier, then converts the byte stream to a pixel stream into a cross
0019 clock domain towards a parallel interface that can be read by a sensor
0020 controller.
0021 IDI interface is Synopsys proprietary.
0022 CSI2DC can act a simple bypass bridge if the incoming data is coming from
0023 a parallel interface.
0024
0025 CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
0026 is connected at the output to a sensor controller and the data pipe is
0027 accessible as a DMA slave port to a DMA controller.
0028
0029 CSI2DC supports a single 'port' node as a sink port with either Synopsys
0030 32-bit IDI interface or a parallel interface.
0031
0032 CSI2DC supports one 'port' node as source port with parallel interface.
0033 This is called video pipe.
0034 This port has an 'endpoint' that can be connected to a sink port of another
0035 controller (next in pipeline).
0036
0037 CSI2DC also supports direct access to the data through AHB, via DMA channel,
0038 called data pipe.
0039 For data pipe to be available, a dma controller and a dma channel must be
0040 referenced.
0041
0042 properties:
0043 compatible:
0044 const: microchip,sama7g5-csi2dc
0045
0046 reg:
0047 maxItems: 1
0048
0049 clocks:
0050 minItems: 2
0051 maxItems: 2
0052
0053 clock-names:
0054 description:
0055 CSI2DC must have two clocks to function correctly. One clock is the
0056 peripheral clock for the inside functionality of the hardware block.
0057 This is named 'pclk'. The second clock must be the cross domain clock,
0058 in which CSI2DC will perform clock crossing. This clock must be fed
0059 by the next controller in pipeline, which usually is a sensor controller.
0060 Normally this clock should be given by this sensor controller who
0061 is also a clock source. This clock is named 'scck', sensor controller clock.
0062 items:
0063 - const: pclk
0064 - const: scck
0065
0066 dmas:
0067 maxItems: 1
0068
0069 dma-names:
0070 const: rx
0071
0072 ports:
0073 $ref: /schemas/graph.yaml#/properties/ports
0074
0075 properties:
0076 port@0:
0077 $ref: /schemas/graph.yaml#/$defs/port-base
0078 description:
0079 Input port node, single endpoint describing the input port.
0080
0081 properties:
0082 endpoint:
0083 $ref: video-interfaces.yaml#
0084 unevaluatedProperties: false
0085 description: Endpoint connected to input device
0086
0087 properties:
0088 bus-type:
0089 enum: [4, 5, 6]
0090 default: 4
0091
0092 bus-width:
0093 enum: [8, 9, 10, 11, 12, 13, 14]
0094 default: 14
0095
0096 clock-noncontinuous:
0097 type: boolean
0098 description:
0099 Presence of this boolean property decides whether clock is
0100 continuous or noncontinuous.
0101
0102 remote-endpoint: true
0103
0104 port@1:
0105 $ref: /schemas/graph.yaml#/$defs/port-base
0106 description:
0107 Output port node, single endpoint describing the output port.
0108
0109 properties:
0110 endpoint:
0111 unevaluatedProperties: false
0112 $ref: video-interfaces.yaml#
0113 description: Endpoint connected to output device
0114
0115 properties:
0116 bus-type:
0117 enum: [5, 6]
0118 default: 5
0119
0120 bus-width:
0121 enum: [8, 9, 10, 11, 12, 13, 14]
0122 default: 14
0123
0124 remote-endpoint: true
0125
0126 required:
0127 - port@0
0128 - port@1
0129
0130 additionalProperties: false
0131
0132 required:
0133 - compatible
0134 - reg
0135 - clocks
0136 - clock-names
0137 - ports
0138
0139 examples:
0140 # Example for connecting to a parallel sensor controller block (video pipe)
0141 # and the input is received from Synopsys IDI interface
0142 - |
0143 csi2dc@e1404000 {
0144 compatible = "microchip,sama7g5-csi2dc";
0145 reg = <0xe1404000 0x500>;
0146 clocks = <&pclk>, <&scck>;
0147 clock-names = "pclk", "scck";
0148
0149 ports {
0150 #address-cells = <1>;
0151 #size-cells = <0>;
0152 port@0 {
0153 reg = <0>; /* must be 0, first child port */
0154 csi2dc_in: endpoint { /* input from IDI interface */
0155 bus-type = <4>; /* MIPI CSI2 D-PHY */
0156 remote-endpoint = <&csi2host_out>;
0157 };
0158 };
0159
0160 port@1 {
0161 reg = <1>; /* must be 1, second child port */
0162 csi2dc_out: endpoint {
0163 remote-endpoint = <&xisc_in>; /* output to sensor controller */
0164 };
0165 };
0166 };
0167 };
0168
0169 # Example for connecting to a DMA master as an AHB slave
0170 # and the input is received from Synopsys IDI interface
0171 - |
0172 #include <dt-bindings/dma/at91.h>
0173 csi2dc@e1404000 {
0174 compatible = "microchip,sama7g5-csi2dc";
0175 reg = <0xe1404000 0x500>;
0176 clocks = <&pclk>, <&scck>;
0177 clock-names = "pclk", "scck";
0178 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>;
0179 dma-names = "rx";
0180
0181 ports {
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184 port@0 {
0185 reg = <0>; /* must be 0, first child port */
0186 csi2dc_input: endpoint { /* input from IDI interface */
0187 remote-endpoint = <&csi2host_out>;
0188 };
0189 };
0190
0191 port@1 {
0192 reg = <1>;
0193 };
0194 };
0195 };
0196
0197 ...
