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OSCL-LXR

 
 

    


0001 * Mediatek Video Processor Unit
0002 
0003 Video Processor Unit is a HW video controller. It controls HW Codec including
0004 H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
0005 
0006 Required properties:
0007   - compatible: "mediatek,mt8173-vpu"
0008   - reg: Must contain an entry for each entry in reg-names.
0009   - reg-names: Must include the following entries:
0010     "tcm": tcm base
0011     "cfg_reg": Main configuration registers base
0012   - interrupts: interrupt number to the cpu.
0013   - clocks : clock name from clock manager
0014   - clock-names: must be main. It is the main clock of VPU
0015 
0016 Optional properties:
0017   - memory-region: phandle to a node describing memory (see
0018     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
0019     to be used for VPU extended memory; if not present, VPU may be located
0020     anywhere in the memory
0021 
0022 Example:
0023         vpu: vpu@10020000 {
0024                 compatible = "mediatek,mt8173-vpu";
0025                 reg = <0 0x10020000 0 0x30000>,
0026                       <0 0x10050000 0 0x100>;
0027                 reg-names = "tcm", "cfg_reg";
0028                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
0029                 clocks = <&topckgen TOP_SCP_SEL>;
0030                 clock-names = "main";
0031         };