0001 * Mediatek Media Data Path
0002
0003 Media Data Path is used for scaling and color space conversion.
0004
0005 Required properties (controller node):
0006 - compatible: "mediatek,mt8173-mdp"
0007 - mediatek,vpu: the node of video processor unit, see
0008 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
0009
0010 Required properties (all function blocks, child node):
0011 - compatible: Should be one of
0012 "mediatek,mt8173-mdp-rdma" - read DMA
0013 "mediatek,mt8173-mdp-rsz" - resizer
0014 "mediatek,mt8173-mdp-wdma" - write DMA
0015 "mediatek,mt8173-mdp-wrot" - write DMA with rotation
0016 - reg: Physical base address and length of the function block register space
0017 - clocks: device clocks, see
0018 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
0019 - power-domains: a phandle to the power domain, see
0020 Documentation/devicetree/bindings/power/power_domain.txt for details.
0021
0022 Required properties (DMA function blocks, child node):
0023 - compatible: Should be one of
0024 "mediatek,mt8173-mdp-rdma"
0025 "mediatek,mt8173-mdp-wdma"
0026 "mediatek,mt8173-mdp-wrot"
0027 - iommus: should point to the respective IOMMU block with master port as
0028 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
0029 for details.
0030
0031 Example:
0032 mdp_rdma0: rdma@14001000 {
0033 compatible = "mediatek,mt8173-mdp-rdma";
0034 "mediatek,mt8173-mdp";
0035 reg = <0 0x14001000 0 0x1000>;
0036 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
0037 <&mmsys CLK_MM_MUTEX_32K>;
0038 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0039 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
0040 mediatek,vpu = <&vpu>;
0041 };
0042
0043 mdp_rdma1: rdma@14002000 {
0044 compatible = "mediatek,mt8173-mdp-rdma";
0045 reg = <0 0x14002000 0 0x1000>;
0046 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
0047 <&mmsys CLK_MM_MUTEX_32K>;
0048 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0049 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
0050 };
0051
0052 mdp_rsz0: rsz@14003000 {
0053 compatible = "mediatek,mt8173-mdp-rsz";
0054 reg = <0 0x14003000 0 0x1000>;
0055 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
0056 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0057 };
0058
0059 mdp_rsz1: rsz@14004000 {
0060 compatible = "mediatek,mt8173-mdp-rsz";
0061 reg = <0 0x14004000 0 0x1000>;
0062 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
0063 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0064 };
0065
0066 mdp_rsz2: rsz@14005000 {
0067 compatible = "mediatek,mt8173-mdp-rsz";
0068 reg = <0 0x14005000 0 0x1000>;
0069 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
0070 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0071 };
0072
0073 mdp_wdma0: wdma@14006000 {
0074 compatible = "mediatek,mt8173-mdp-wdma";
0075 reg = <0 0x14006000 0 0x1000>;
0076 clocks = <&mmsys CLK_MM_MDP_WDMA>;
0077 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0078 iommus = <&iommu M4U_PORT_MDP_WDMA>;
0079 };
0080
0081 mdp_wrot0: wrot@14007000 {
0082 compatible = "mediatek,mt8173-mdp-wrot";
0083 reg = <0 0x14007000 0 0x1000>;
0084 clocks = <&mmsys CLK_MM_MDP_WROT0>;
0085 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0086 iommus = <&iommu M4U_PORT_MDP_WROT0>;
0087 };
0088
0089 mdp_wrot1: wrot@14008000 {
0090 compatible = "mediatek,mt8173-mdp-wrot";
0091 reg = <0 0x14008000 0 0x1000>;
0092 clocks = <&mmsys CLK_MM_MDP_WROT1>;
0093 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0094 iommus = <&iommu M4U_PORT_MDP_WROT1>;
0095 };
