0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Mediatek Video Decode Accelerator With Multi Hardware
0009
0010 maintainers:
0011 - Yunfei Dong <yunfei.dong@mediatek.com>
0012
0013 description: |
0014 Mediatek Video Decode is the video decode hardware present in Mediatek
0015 SoCs which supports high resolution decoding functionalities. Required
0016 parent and child device node.
0017
0018 About the Decoder Hardware Block Diagram, please check below:
0019
0020 +------------------------------------------------+-------------------------------------+
0021 | | |
0022 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
0023 | || || | || |
0024 +------------||-------------||-------------------+---------------------||--------------+
0025 || lat || | core workqueue <parent>
0026 -------------||-------------||-------------------|---------------------||---------------
0027 ||<------------||----------------HW index---------------->|| <child>
0028 \/ \/ \/
0029 +-------------------------------------------------------------+
0030 | enable/disable |
0031 | clk power irq iommu |
0032 | (lat/lat soc/core0/core1) |
0033 +-------------------------------------------------------------+
0034
0035 As above, there are parent and child devices, child mean each hardware. The child device
0036 controls the information of each hardware independent which include clk/power/irq.
0037
0038 There are two workqueues in parent device: lat workqueue and core workqueue. They are used
0039 to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
0040 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
0041 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
0042 writing the result to output buffer, disable hardware when core decode done. These two
0043 hardwares will decode each frame cyclically.
0044
0045 For the smi common may not the same for each hardware, can't combine all hardware in one node,
0046 or leading to iommu fault when access dram data.
0047
0048 Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
0049 platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
0050 clock when lat start to work, don't have interrupt.
0051
0052 mt8195: lat soc HW + lat HW + core HW
0053 mt8192: lat HW + core HW
0054
0055 properties:
0056 compatible:
0057 enum:
0058 - mediatek,mt8192-vcodec-dec
0059 - mediatek,mt8186-vcodec-dec
0060 - mediatek,mt8195-vcodec-dec
0061
0062 reg:
0063 maxItems: 1
0064
0065 iommus:
0066 minItems: 1
0067 maxItems: 32
0068 description: |
0069 List of the hardware port in respective IOMMU block for current Socs.
0070 Refer to bindings/iommu/mediatek,iommu.yaml.
0071
0072 mediatek,scp:
0073 $ref: /schemas/types.yaml#/definitions/phandle
0074 description: |
0075 The node of system control processor (SCP), using
0076 the remoteproc & rpmsg framework.
0077
0078 dma-ranges:
0079 maxItems: 1
0080 description: |
0081 Describes the physical address space of IOMMU maps to memory.
0082
0083 "#address-cells":
0084 const: 2
0085
0086 "#size-cells":
0087 const: 2
0088
0089 ranges: true
0090
0091 # Required child node:
0092 patternProperties:
0093 '^vcodec-lat@[0-9a-f]+$':
0094 type: object
0095
0096 properties:
0097 compatible:
0098 enum:
0099 - mediatek,mtk-vcodec-lat
0100 - mediatek,mtk-vcodec-lat-soc
0101
0102 reg:
0103 maxItems: 1
0104
0105 interrupts:
0106 maxItems: 1
0107
0108 iommus:
0109 minItems: 1
0110 maxItems: 32
0111 description: |
0112 List of the hardware port in respective IOMMU block for current Socs.
0113 Refer to bindings/iommu/mediatek,iommu.yaml.
0114
0115 clocks:
0116 maxItems: 5
0117
0118 clock-names:
0119 items:
0120 - const: sel
0121 - const: soc-vdec
0122 - const: soc-lat
0123 - const: vdec
0124 - const: top
0125
0126 assigned-clocks:
0127 maxItems: 1
0128
0129 assigned-clock-parents:
0130 maxItems: 1
0131
0132 power-domains:
0133 maxItems: 1
0134
0135 required:
0136 - compatible
0137 - reg
0138 - iommus
0139 - clocks
0140 - clock-names
0141 - assigned-clocks
0142 - assigned-clock-parents
0143 - power-domains
0144
0145 additionalProperties: false
0146
0147 '^vcodec-core@[0-9a-f]+$':
0148 type: object
0149
0150 properties:
0151 compatible:
0152 const: mediatek,mtk-vcodec-core
0153
0154 reg:
0155 maxItems: 1
0156
0157 interrupts:
0158 maxItems: 1
0159
0160 iommus:
0161 minItems: 1
0162 maxItems: 32
0163 description: |
0164 List of the hardware port in respective IOMMU block for current Socs.
0165 Refer to bindings/iommu/mediatek,iommu.yaml.
0166
0167 clocks:
0168 maxItems: 5
0169
0170 clock-names:
0171 items:
0172 - const: sel
0173 - const: soc-vdec
0174 - const: soc-lat
0175 - const: vdec
0176 - const: top
0177
0178 assigned-clocks:
0179 maxItems: 1
0180
0181 assigned-clock-parents:
0182 maxItems: 1
0183
0184 power-domains:
0185 maxItems: 1
0186
0187 required:
0188 - compatible
0189 - reg
0190 - interrupts
0191 - iommus
0192 - clocks
0193 - clock-names
0194 - assigned-clocks
0195 - assigned-clock-parents
0196 - power-domains
0197
0198 additionalProperties: false
0199
0200 required:
0201 - compatible
0202 - reg
0203 - iommus
0204 - mediatek,scp
0205 - dma-ranges
0206 - ranges
0207
0208 if:
0209 properties:
0210 compatible:
0211 contains:
0212 enum:
0213 - mediatek,mtk-vcodec-lat
0214
0215 then:
0216 required:
0217 - interrupts
0218
0219 additionalProperties: false
0220
0221 examples:
0222 - |
0223 #include <dt-bindings/interrupt-controller/arm-gic.h>
0224 #include <dt-bindings/memory/mt8192-larb-port.h>
0225 #include <dt-bindings/interrupt-controller/irq.h>
0226 #include <dt-bindings/clock/mt8192-clk.h>
0227 #include <dt-bindings/power/mt8192-power.h>
0228
0229 bus@16000000 {
0230 #address-cells = <2>;
0231 #size-cells = <2>;
0232 ranges = <0 0x16000000 0x16000000 0 0x40000>;
0233
0234 video-codec@16000000 {
0235 compatible = "mediatek,mt8192-vcodec-dec";
0236 mediatek,scp = <&scp>;
0237 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
0238 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
0239 #address-cells = <2>;
0240 #size-cells = <2>;
0241 ranges = <0 0 0 0x16000000 0 0x40000>;
0242 reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
0243 vcodec-lat@10000 {
0244 compatible = "mediatek,mtk-vcodec-lat";
0245 reg = <0 0x10000 0 0x800>;
0246 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
0247 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
0248 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
0249 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
0250 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
0251 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
0252 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
0253 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
0254 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
0255 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
0256 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
0257 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
0258 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
0259 <&topckgen CLK_TOP_MAINPLL_D4>;
0260 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
0261 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
0262 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
0263 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
0264 };
0265
0266 vcodec-core@25000 {
0267 compatible = "mediatek,mtk-vcodec-core";
0268 reg = <0 0x25000 0 0x1000>;
0269 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
0270 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
0271 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
0272 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
0273 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
0274 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
0275 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
0276 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
0277 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
0278 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
0279 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
0280 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
0281 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
0282 <&vdecsys CLK_VDEC_VDEC>,
0283 <&vdecsys CLK_VDEC_LAT>,
0284 <&vdecsys CLK_VDEC_LARB1>,
0285 <&topckgen CLK_TOP_MAINPLL_D4>;
0286 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
0287 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
0288 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
0289 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
0290 };
0291 };
0292 };
