bindings/media/mediatek%2Cvcodec-encoder.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Mediatek Video Encode Accelerator
0009
0010 maintainers:
0011   - Yunfei Dong <yunfei.dong@mediatek.com>
0012
0013 description: |+
0014   Mediatek Video Encode is the video encode hardware present in Mediatek
0015   SoCs which supports high resolution encoding functionalities.
0016
0017 properties:
0018   compatible:
0019     enum:
0020       - mediatek,mt8173-vcodec-enc-vp8
0021       - mediatek,mt8173-vcodec-enc
0022       - mediatek,mt8183-vcodec-enc
0023       - mediatek,mt8192-vcodec-enc
0024       - mediatek,mt8195-vcodec-enc
0025
0026   reg:
0027     maxItems: 1
0028
0029   interrupts:
0030     maxItems: 1
0031
0032   clocks:
0033     minItems: 1
0034     maxItems: 5
0035
0036   clock-names:
0037     minItems: 1
0038     maxItems: 5
0039
0040   assigned-clocks: true
0041
0042   assigned-clock-parents: true
0043
0044   iommus:
0045     minItems: 1
0046     maxItems: 32
0047     description: |
0048       List of the hardware port in respective IOMMU block for current Socs.
0049       Refer to bindings/iommu/mediatek,iommu.yaml.
0050
0051   dma-ranges:
0052     maxItems: 1
0053     description: |
0054       Describes the physical address space of IOMMU maps to memory.
0055
0056   mediatek,vpu:
0057     $ref: /schemas/types.yaml#/definitions/phandle
0058     description:
0059       Describes point to vpu.
0060
0061   mediatek,scp:
0062     $ref: /schemas/types.yaml#/definitions/phandle
0063     description:
0064       Describes point to scp.
0065
0066   power-domains:
0067     maxItems: 1
0068
0069 required:
0070   - compatible
0071   - reg
0072   - interrupts
0073   - clocks
0074   - clock-names
0075   - iommus
0076   - assigned-clocks
0077   - assigned-clock-parents
0078
0079 allOf:
0080   - if:
0081       properties:
0082         compatible:
0083           contains:
0084             enum:
0085               - mediatek,mt8183-vcodec-enc
0086               - mediatek,mt8192-vcodec-enc
0087
0088     then:
0089       required:
0090         - mediatek,scp
0091
0092   - if:
0093       properties:
0094         compatible:
0095           contains:
0096             enum:
0097               - mediatek,mt8173-vcodec-enc-vp8
0098               - mediatek,mt8173-vcodec-enc
0099
0100     then:
0101       required:
0102         - mediatek,vpu
0103
0104   - if:
0105       properties:
0106         compatible:
0107           enum:
0108             - mediatek,mt8173-vcodec-enc
0109             - mediatek,mt8192-vcodec-enc
0110
0111     then:
0112       properties:
0113         clock:
0114           items:
0115             minItems: 1
0116             maxItems: 1
0117         clock-names:
0118           items:
0119             - const: venc_sel
0120     else:  # for vp8 hw decoder
0121       properties:
0122         clock:
0123           items:
0124             minItems: 1
0125             maxItems: 1
0126         clock-names:
0127           items:
0128             - const: venc_lt_sel
0129
0130 additionalProperties: false
0131
0132 examples:
0133   - |
0134     #include <dt-bindings/interrupt-controller/arm-gic.h>
0135     #include <dt-bindings/clock/mt8173-clk.h>
0136     #include <dt-bindings/memory/mt8173-larb-port.h>
0137     #include <dt-bindings/interrupt-controller/irq.h>
0138
0139     vcodec_enc_avc: vcodec@18002000 {
0140       compatible = "mediatek,mt8173-vcodec-enc";
0141       reg = <0x18002000 0x1000>;
0142       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
0143       iommus = <&iommu M4U_PORT_VENC_RCPU>,
0144              <&iommu M4U_PORT_VENC_REC>,
0145              <&iommu M4U_PORT_VENC_BSDMA>,
0146              <&iommu M4U_PORT_VENC_SV_COMV>,
0147              <&iommu M4U_PORT_VENC_RD_COMV>,
0148              <&iommu M4U_PORT_VENC_CUR_LUMA>,
0149              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
0150              <&iommu M4U_PORT_VENC_REF_LUMA>,
0151              <&iommu M4U_PORT_VENC_REF_CHROMA>,
0152              <&iommu M4U_PORT_VENC_NBM_RDMA>,
0153              <&iommu M4U_PORT_VENC_NBM_WDMA>;
0154       mediatek,vpu = <&vpu>;
0155       clocks = <&topckgen CLK_TOP_VENC_SEL>;
0156       clock-names = "venc_sel";
0157       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
0158       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
0159     };
0160
0161     vcodec_enc_vp8: vcodec@19002000 {
0162       compatible = "mediatek,mt8173-vcodec-enc-vp8";
0163       reg =  <0x19002000 0x1000>;       /* VENC_LT_SYS */
0164       interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
0165       iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
0166              <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
0167              <&iommu M4U_PORT_VENC_BSDMA_SET2>,
0168              <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
0169              <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
0170              <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
0171              <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
0172              <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
0173              <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
0174       mediatek,vpu = <&vpu>;
0175       clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
0176       clock-names = "venc_lt_sel";
0177       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
0178       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
0179     };