0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Mediatek Video Decode Accelerator
0009
0010 maintainers:
0011 - Yunfei Dong <yunfei.dong@mediatek.com>
0012
0013 description: |+
0014 Mediatek Video Decode is the video decode hardware present in Mediatek
0015 SoCs which supports high resolution decoding functionalities.
0016
0017 properties:
0018 compatible:
0019 enum:
0020 - mediatek,mt8173-vcodec-dec
0021 - mediatek,mt8183-vcodec-dec
0022
0023 reg:
0024 maxItems: 12
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 maxItems: 8
0031
0032 clock-names:
0033 items:
0034 - const: vcodecpll
0035 - const: univpll_d2
0036 - const: clk_cci400_sel
0037 - const: vdec_sel
0038 - const: vdecpll
0039 - const: vencpll
0040 - const: venc_lt_sel
0041 - const: vdec_bus_clk_src
0042
0043 assigned-clocks: true
0044
0045 assigned-clock-parents: true
0046
0047 assigned-clock-rates: true
0048
0049 power-domains:
0050 maxItems: 1
0051
0052 iommus:
0053 minItems: 1
0054 maxItems: 32
0055 description: |
0056 List of the hardware port in respective IOMMU block for current Socs.
0057 Refer to bindings/iommu/mediatek,iommu.yaml.
0058
0059 dma-ranges:
0060 maxItems: 1
0061 description: |
0062 Describes the physical address space of IOMMU maps to memory.
0063
0064 mediatek,vpu:
0065 $ref: /schemas/types.yaml#/definitions/phandle
0066 description:
0067 Describes point to vpu.
0068
0069 mediatek,scp:
0070 $ref: /schemas/types.yaml#/definitions/phandle
0071 description:
0072 Describes point to scp.
0073
0074 required:
0075 - compatible
0076 - reg
0077 - interrupts
0078 - clocks
0079 - clock-names
0080 - iommus
0081 - assigned-clocks
0082 - assigned-clock-parents
0083
0084 allOf:
0085 - if:
0086 properties:
0087 compatible:
0088 contains:
0089 enum:
0090 - mediatek,mt8183-vcodec-dec
0091
0092 then:
0093 required:
0094 - mediatek,scp
0095
0096 - if:
0097 properties:
0098 compatible:
0099 contains:
0100 enum:
0101 - mediatek,mt8173-vcodec-dec
0102
0103 then:
0104 required:
0105 - mediatek,vpu
0106
0107 additionalProperties: false
0108
0109 examples:
0110 - |
0111 #include <dt-bindings/interrupt-controller/arm-gic.h>
0112 #include <dt-bindings/clock/mt8173-clk.h>
0113 #include <dt-bindings/memory/mt8173-larb-port.h>
0114 #include <dt-bindings/interrupt-controller/irq.h>
0115 #include <dt-bindings/power/mt8173-power.h>
0116
0117 vcodec_dec: vcodec@16000000 {
0118 compatible = "mediatek,mt8173-vcodec-dec";
0119 reg = <0x16000000 0x100>, /*VDEC_SYS*/
0120 <0x16020000 0x1000>, /*VDEC_MISC*/
0121 <0x16021000 0x800>, /*VDEC_LD*/
0122 <0x16021800 0x800>, /*VDEC_TOP*/
0123 <0x16022000 0x1000>, /*VDEC_CM*/
0124 <0x16023000 0x1000>, /*VDEC_AD*/
0125 <0x16024000 0x1000>, /*VDEC_AV*/
0126 <0x16025000 0x1000>, /*VDEC_PP*/
0127 <0x16026800 0x800>, /*VP8_VD*/
0128 <0x16027000 0x800>, /*VP6_VD*/
0129 <0x16027800 0x800>, /*VP8_VL*/
0130 <0x16028400 0x400>; /*VP9_VD*/
0131 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
0132 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
0133 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
0134 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
0135 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
0136 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
0137 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
0138 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
0139 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
0140 mediatek,vpu = <&vpu>;
0141 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
0142 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
0143 <&topckgen CLK_TOP_UNIVPLL_D2>,
0144 <&topckgen CLK_TOP_CCI400_SEL>,
0145 <&topckgen CLK_TOP_VDEC_SEL>,
0146 <&topckgen CLK_TOP_VCODECPLL>,
0147 <&apmixedsys CLK_APMIXED_VENCPLL>,
0148 <&topckgen CLK_TOP_VENC_LT_SEL>,
0149 <&topckgen CLK_TOP_VCODECPLL_370P5>;
0150 clock-names = "vcodecpll",
0151 "univpll_d2",
0152 "clk_cci400_sel",
0153 "vdec_sel",
0154 "vdecpll",
0155 "vencpll",
0156 "venc_lt_sel",
0157 "vdec_bus_clk_src";
0158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
0159 <&topckgen CLK_TOP_CCI400_SEL>,
0160 <&topckgen CLK_TOP_VDEC_SEL>,
0161 <&apmixedsys CLK_APMIXED_VCODECPLL>,
0162 <&apmixedsys CLK_APMIXED_VENCPLL>;
0163 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
0164 <&topckgen CLK_TOP_UNIVPLL_D2>,
0165 <&topckgen CLK_TOP_VCODECPLL>;
0166 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
0167 };
